Cpre584 - User contributions [en]

Using ISE's Core Generator to build FIFOs and other IP cores

2013-02-26T23:59:49Z

Tyler07: /* Simulating IP Cores With Modelsim (For a Custom Testbench) */

== Why Use Dedicated Logic ==
If you don't use it, you lose it! Don't let the dedicated logic (BRAMs, DSP slices) go unused... you'll hurt their feelings.

Dedicated logic improves compile times and reduces the amount of Slice Logic used. It's also FAST, and can help reduce the chance of timing errors. For example, the DSP slices can operate at 550 MHz.

== How-to ==
# Open Xilinx's ISE from the terminal (make sure your [[Convey environment setup | environmental variables]] are set):
ise &
# Create or open a project. The devices on the HC-1 and HC-2 are Virtex 5 FPGAs (xc5vlx330, -2, ff1760).
# Open the Core Generator (Tools -> Core Generator...)
# Create a new Core Generator project.
## Part
### Family: Virtex5
### Device: xc5vlx330
### Package: ff1760
### Speed: -2
## Generation
### Simulation Model: Structural
# Generate you IP Cores!
# Create folder named "coregen" in your PDK proejct
# Copy the .ngc, .v, and .xco to the coregen folder in your PDK project

== Common IP Cores ==
Most IP cores can be implemented using either BRAM (Block RAM), DSP cores, or Slice logic. To give you an idea about the number of components available, there are:
* 288 36-Kilobit BRAMs available
** BRAMs are dual port, allowing multiple small FIFOs per BRAM
* 28x15 DSP slices
* 51,840 Slices (each slice contains 4 LUTS & 4 Flip-flops)

Here are some common components you could use:
* Memories & Storage Elements -> (use Block RAM)
** FIFOs (any port width)
** Dual port RAM (port widths: 2, 4, 8... up to 128 bits)
* Math Functions -> (use DSP slices)
** Adder/Subtracts (up to 48 bit)
** Multipliers (up to 64 bit, 128 bit output)
** Dividers (up to 32 bit)

==Simulating IP Cores With Modelsim (For a Custom Testbench)==
So you have just used coregen to make your IP core and you would like to use it in your testbench. The steps below will show you how you can successfully simulate the IP core.
*Add the .v or .vhd files to your Modelsim project so that when they are compilied they show up in your work
*At the top of the module that you will be using to instantiate the new IP core, add the following:
**Library UNISIM;
**USE UNISIM.VCOMPONENTS.ALL;
*Now in the Modelsim console run the following command:
**vmap <library> <path to library>
**For our purposes this will be:
***VHDL - vmap unisim /remote/Xilinx/13.4/ISE/vhdl/mti_se/10.1c/lin64/unisim/
***Verilog - vmap unisim /remote/Xilinx/13.4/ISE/verilog/mti_se/10.1c/lin64/unisim/
*If your corgen module depends on the xilinxcorelib you will also want to map this library
**vmap xilinxcorelib /remote/Xilinx/13.4/ISE/vhdl/mti_se/10.1c/lin64/xilinxcorelib
(These paths are subject to change, they were added on 2/14/13)

Using ISE's Core Generator to build FIFOs and other IP cores

2013-02-26T23:59:24Z

Tyler07: /* Simulating IP Cores With Modelsim (For a Custom Testbench) */

== Why Use Dedicated Logic ==
If you don't use it, you lose it! Don't let the dedicated logic (BRAMs, DSP slices) go unused... you'll hurt their feelings.

Dedicated logic improves compile times and reduces the amount of Slice Logic used. It's also FAST, and can help reduce the chance of timing errors. For example, the DSP slices can operate at 550 MHz.

== How-to ==
# Open Xilinx's ISE from the terminal (make sure your [[Convey environment setup | environmental variables]] are set):
ise &
# Create or open a project. The devices on the HC-1 and HC-2 are Virtex 5 FPGAs (xc5vlx330, -2, ff1760).
# Open the Core Generator (Tools -> Core Generator...)
# Create a new Core Generator project.
## Part
### Family: Virtex5
### Device: xc5vlx330
### Package: ff1760
### Speed: -2
## Generation
### Simulation Model: Structural
# Generate you IP Cores!
# Create folder named "coregen" in your PDK proejct
# Copy the .ngc, .v, and .xco to the coregen folder in your PDK project

== Common IP Cores ==
Most IP cores can be implemented using either BRAM (Block RAM), DSP cores, or Slice logic. To give you an idea about the number of components available, there are:
* 288 36-Kilobit BRAMs available
** BRAMs are dual port, allowing multiple small FIFOs per BRAM
* 28x15 DSP slices
* 51,840 Slices (each slice contains 4 LUTS & 4 Flip-flops)

Here are some common components you could use:
* Memories & Storage Elements -> (use Block RAM)
** FIFOs (any port width)
** Dual port RAM (port widths: 2, 4, 8... up to 128 bits)
* Math Functions -> (use DSP slices)
** Adder/Subtracts (up to 48 bit)
** Multipliers (up to 64 bit, 128 bit output)
** Dividers (up to 32 bit)

==Simulating IP Cores With Modelsim (For a Custom Testbench)==
So you have just used coregen to make your IP core and you would like to use it in your testbench. The steps below will show you how you can successfully simulate the IP core.
*Add the .v or .vhd files to your Modelsim project so that when they are compilied they show up in your work
*At the top of the module that you will be using to instantiate the new IP core, add the following:
**Library UNISIM;
**USE UNISIM.VCOMPONENTS.ALL;
*Now in the Modelsim console run the following command:
**vmap <library> <path to library>
**For our purposes this will be:
***VHDL - vmap unisim /remote/Xilinx/13.4/ISE/vhdl/mti_se/10.1c/lin64/unisim/
***Verilog - vmap unisim /remote/Xilinx/13.4/ISE/verilog/mti_se/10.1c/lin64/unisim/
*If your corgen module depends on the xilinxcorelib you will also want to make this library
**vmap xilinxcorelib /remote/Xilinx/13.4/ISE/vhdl/mti_se/10.1c/lin64/xilinxcorelib
(These paths are subject to change, they were added on 2/14/13)

Using ISE's Core Generator to build FIFOs and other IP cores

2013-02-17T22:57:16Z

Tyler07: /* Simulating IP Cores With Modelsim (For a Custom Testbench) */

== Why Use Dedicated Logic ==
If you don't use it, you lose it! Don't let the dedicated logic (BRAMs, DSP slices) go unused... you'll hurt their feelings.

Dedicated logic improves compile times and reduces the amount of Slice Logic used. It's also FAST, and can help reduce the chance of timing errors. For example, the DSP slices can operate at 550 MHz.

== How-to ==
# Open Xilinx's ISE from the terminal (make sure your [[Convey environment setup | environmental variables]] are set):
ise &
# Create or open a project. The devices on the HC-1 and HC-2 are Virtex 5 FPGAs (xc5vlx330, -2, ff1760).
# Open the Core Generator (Tools -> Core Generator...)
# Create a new Core Generator project.
## Part
### Family: Virtex5
### Device: xc5vlx330
### Package: ff1760
### Speed: -2
## Generation
### Simulation Model: Structural
# Generate you IP Cores!
# Create folder named "coregen" in your PDK proejct
# Copy the .ngc, .v, and .xco to the coregen folder in your PDK project

== Common IP Cores ==
Most IP cores can be implemented using either BRAM (Block RAM), DSP cores, or Slice logic. To give you an idea about the number of components available, there are:
* 288 36-Kilobit BRAMs available
** BRAMs are dual port, allowing multiple small FIFOs per BRAM
* 28x15 DSP slices
* 51,840 Slices (each slice contains 4 LUTS & 4 Flip-flops)

Here are some common components you could use:
* Memories & Storage Elements -> (use Block RAM)
** FIFOs (any port width)
** Dual port RAM (port widths: 2, 4, 8... up to 128 bits)
* Math Functions -> (use DSP slices)
** Adder/Subtracts (up to 48 bit)
** Multipliers (up to 64 bit, 128 bit output)
** Dividers (up to 32 bit)

==Simulating IP Cores With Modelsim (For a Custom Testbench)==
So you have just used coregen to make your IP core and you would like to use it in your testbench. The steps below will show you how you can successfully simulate the IP core.
*Add the .v or .vhd files to your Modelsim project so that when they are compilied they show up in your work
*At the top of the module that you will be using to instantiate the new IP core, add the following:
**Library UNISIM;
**USE UNISIM.VCOMPONENTS.ALL;
*Now in the Modelsim console run the following command:
**vmap <library> <path to library>
**For our purposes this will be:
***VHDL - vmap unisim /remote/Xilinx/13.4/ISE/vhdl/mti_se/10.1c/lin64/unisim/
***Verilog - vmap unisim /remote/Xilinx/13.4/ISE/verilog/mti_se/10.1c/lin64/unisim/
(These paths are subject to change, they were added on 2/14/13)

Team Cyc05

2013-02-15T04:40:54Z

Tyler07: /* Tyler */

{| border="1" cellpadding="5" cellspacing="0" align="right"
|+'''Team Cyc05'''
|-
| align="center" width="200px" | [[Image:Cy.jpg]]
|-
! style="background:#CD1014;" | Cyc05 Team Logo
|-
|-
| colspan="2" align="center" |
{| border="0"
|+''Team Members''
|-
| Osama G. Attia (ogamal)
|-
| Tyler Johnson (tyler07)
|-
| PengQing Xie (carterp)
|}
|}

== Team Members ==
* Osama G. Attia
* Tyler Johnson
* PengQing Xie

== Weekly Presentations ==
*Week 1 - [[Media:Cyc05_-_Presentation_01.pdf | Presentation Slides Week 1]]
*Week 2 - [[Media:Cyc05_Week_2.pdf | Presentation Slides Week 2]]
*Week 3 - [[Media:Cyc05_week3_presentation.pdf‎ | Presentation Slides Week 3]]
*Week 4 - [[Media:Cyc05_week4_presentation.pdf‎ | Presentation Slides Week 4]]

== Wiki Contributions ==
=== Tyler ===
*Week 1
**[[Useful Modelsim Commands]]
**[[Media:Modelsim_pe_user_10.0d.pdf | Modelsim Users Guide]]
*Week2
** [[Media:Connect_Remotely_Via_VPN.pdf | Guide to Remote Connecting]]
*Week3
**[[Adding VHDL Files to a Project]] Additions and alterations
**Hosted the scripts for Kevinss tutorial and provided a link for it
**Modified the landing page to Kevni't tutorial to have the pdf, and a link to the scripts
**Modified [[Tutorial: Creating a Custom Bitfile]], some details were unclear and/or left out about using your newly built bitfile
*Week 4
**Added a topic to the FAQ page regarding how you can use the /tmp/ directory in order to speed up certain activities such as building a bitfile or simulation. Added [[Media:UseTmpScript.sh‎ | this script]] to help with migration.
*Week 5
**Added instructions for simulating an IP core made with ISE corgen. This is mostly for when you would like to use your own testbench, I believe Coney's testbench will work without these steps
***[[Using ISE's Core Generator to build FIFOs and other IP cores]]

=== Osama ===
*Week 1: Creating Team Cyc05 page.
*Week 2:
**Updating [[Connecting to convey-1.ece.iastate.edu]] with usage policy
**Adding [[Frequently Asked Questions]] page
* Week 3:
**Updating the [[Frequently Asked Questions]] page
**Adding and maintaining the [[Using the Memory Controller Interface]] page
* Week 4:
**[[Media:Vhd2v isnt.txt|Python script to generate instantiation code of VHDL module in Verilog]]
**[[Media:Convey_mc_ports.txt|Python script to generate the MC interface signals in VHDL]]
**[[Media:convey_mc_ports_vhdl.txt|MC interface signals]] in VHDL
**Adding more stuff to the [[Frequently Asked Questions]] page

=== PengQing ===
*Week 1:
**[http://sn0v.wordpress.com/2012/12/07/installing-cuda-5-on-ubuntu-12-04/ Installing CUDA on Ubuntu]
**[http://graphics.stanford.edu/~mhouston/public_talks/R520-mhouston.pdf General Purpose Computation on GPUs (GPGPU)]
*Week 2:
**[http://vol.verilog.com/VOL/main.htm Verilog self-study online course]
*Week 3:
**[http://www.ece.msstate.edu/~reese/EE4743/lectures/verilog_intro_2002/verilog_intro_2002.pdf Verilog vs. VHDL]
*Week 4:
**[http://www.vogella.com/articles/Git/article.html git tutorial]

Team Cyc05

2013-02-15T04:40:25Z

Tyler07: /* Tyler */

{| border="1" cellpadding="5" cellspacing="0" align="right"
|+'''Team Cyc05'''
|-
| align="center" width="200px" | [[Image:Cy.jpg]]
|-
! style="background:#CD1014;" | Cyc05 Team Logo
|-
|-
| colspan="2" align="center" |
{| border="0"
|+''Team Members''
|-
| Osama G. Attia (ogamal)
|-
| Tyler Johnson (tyler07)
|-
| PengQing Xie (carterp)
|}
|}

== Team Members ==
* Osama G. Attia
* Tyler Johnson
* PengQing Xie

== Weekly Presentations ==
*Week 1 - [[Media:Cyc05_-_Presentation_01.pdf | Presentation Slides Week 1]]
*Week 2 - [[Media:Cyc05_Week_2.pdf | Presentation Slides Week 2]]
*Week 3 - [[Media:Cyc05_week3_presentation.pdf‎ | Presentation Slides Week 3]]
*Week 4 - [[Media:Cyc05_week4_presentation.pdf‎ | Presentation Slides Week 4]]

== Wiki Contributions ==
=== Tyler ===
*Week 1
**[[Useful Modelsim Commands]]
**[[Media:Modelsim_pe_user_10.0d.pdf | Modelsim Users Guide]]
*Week2
** [[Media:Connect_Remotely_Via_VPN.pdf | Guide to Remote Connecting]]
*Week3
**[[Adding VHDL Files to a Project]] Additions and alterations
**Hosted the scripts for Kevinss tutorial and provided a link for it
**Modified the landing page to Kevni't tutorial to have the pdf, and a link to the scripts
**Modified [[Tutorial: Creating a Custom Bitfile]], some details were unclear and/or left out about using your newly built bitfile
*Week 4
**Added a topic to the FAQ page regarding how you can use the /tmp/ directory in order to speed up certain activities such as building a bitfile or simulation. Added [[Media:UseTmpScript.sh‎ | this script]] to help with migration.
*Week 5
**Added instructions for simulating an IP core made with ISE corgen. This is mostly for when you would like to use your own testbench, I believe Coney's testbench will work without these steps
***[[]]

=== Osama ===
*Week 1: Creating Team Cyc05 page.
*Week 2:
**Updating [[Connecting to convey-1.ece.iastate.edu]] with usage policy
**Adding [[Frequently Asked Questions]] page
* Week 3:
**Updating the [[Frequently Asked Questions]] page
**Adding and maintaining the [[Using the Memory Controller Interface]] page
* Week 4:
**[[Media:Vhd2v isnt.txt|Python script to generate instantiation code of VHDL module in Verilog]]
**[[Media:Convey_mc_ports.txt|Python script to generate the MC interface signals in VHDL]]
**[[Media:convey_mc_ports_vhdl.txt|MC interface signals]] in VHDL
**Adding more stuff to the [[Frequently Asked Questions]] page

=== PengQing ===
*Week 1:
**[http://sn0v.wordpress.com/2012/12/07/installing-cuda-5-on-ubuntu-12-04/ Installing CUDA on Ubuntu]
**[http://graphics.stanford.edu/~mhouston/public_talks/R520-mhouston.pdf General Purpose Computation on GPUs (GPGPU)]
*Week 2:
**[http://vol.verilog.com/VOL/main.htm Verilog self-study online course]
*Week 3:
**[http://www.ece.msstate.edu/~reese/EE4743/lectures/verilog_intro_2002/verilog_intro_2002.pdf Verilog vs. VHDL]
*Week 4:
**[http://www.vogella.com/articles/Git/article.html git tutorial]

Using ISE's Core Generator to build FIFOs and other IP cores

2013-02-15T04:38:20Z

Tyler07:

== Why Use Dedicated Logic ==
If you don't use it, you lose it! Don't let the dedicated logic (BRAMs, DSP slices) go unused... you'll hurt their feelings.

Dedicated logic improves compile times and reduces the amount of Slice Logic used. It's also FAST, and can help reduce the chance of timing errors. For example, the DSP slices can operate at 550 MHz.

== How-to ==
# Open Xilinx's ISE from the terminal (make sure your [[Convey environment setup | environmental variables]] are set):
ise &
# Create or open a project. The devices on the HC-1 and HC-2 are Virtex 5 FPGAs (xc5vlx330, -2, ff1760).
# Open the Core Generator (Tools -> Core Generator...)
# Create a new Core Generator project.
## Part
### Family: Virtex5
### Device: xc5vlx330
### Package: ff1760
### Speed: -2
## Generation
### Simulation Model: Structural
# Generate you IP Cores!
# Create folder named "coregen" in your PDK proejct
# Copy the .ngc, .v, and .xco to the coregen folder in your PDK project

== Common IP Cores ==
Most IP cores can be implemented using either BRAM (Block RAM), DSP cores, or Slice logic. To give you an idea about the number of components available, there are:
* 288 36-Kilobit BRAMs available
** BRAMs are dual port, allowing multiple small FIFOs per BRAM
* 28x15 DSP slices
* 51,840 Slices (each slice contains 4 LUTS & 4 Flip-flops)

Here are some common components you could use:
* Memories & Storage Elements -> (use Block RAM)
** FIFOs (any port width)
** Dual port RAM (port widths: 2, 4, 8... up to 128 bits)
* Math Functions -> (use DSP slices)
** Adder/Subtracts (up to 48 bit)
** Multipliers (up to 64 bit, 128 bit output)
** Dividers (up to 32 bit)

==Simulating IP Cores With Modelsim (For a Custom Testbench)==
So you have just used coregen to make your IP core and you would like to use it in your testbench. The steps below will show you how you can successfully simulate the IP core.
*Add the .v or .vhd files to your Modelsim project so that when they are compilied they show up in your work
*At the top of the module that you will be using to instantiate the new IP core, add the following:
**Library UNISIM;
**USE UNISIM.VCOMPONENTS.ALL;
*Now in the Modelsim console run the following command:
**vmap <library> <path to library>
**For our purposes this will be:
***vmap unisim /remote/Xilinx/13.4/ISE/vhdl/mti_se/10.1c/lin64/unisim/ (This path is subject to change, it was added on 2/14/13)

Team Cyc05

2013-02-12T23:05:38Z

Tyler07: /* Tyler */

{| border="1" cellpadding="5" cellspacing="0" align="right"
|+'''Team Cyc05'''
|-
| align="center" width="200px" | [[Image:Cy.jpg]]
|-
! style="background:#CD1014;" | Cyc05 Team Logo
|-
|-
| colspan="2" align="center" |
{| border="0"
|+''Team Members''
|-
| Osama G. Attia (ogamal)
|-
| Tyler Johnson (tyler07)
|-
| PengQing Xie (carterp)
|}
|}

== Team Members ==
* Osama G. Attia
* Tyler Johnson
* PengQing Xie

== Weekly Presentations ==
*Week 1 - [[Media:Cyc05_-_Presentation_01.pdf | Presentation Slides Week 1]]
*Week 2 - [[Media:Cyc05_Week_2.pdf | Presentation Slides Week 2]]
*Week 3 - [[Media:Cyc05_week3_presentation.pdf‎ | Presentation Slides Week 3]]

== Wiki Contributions ==
=== Tyler ===
*Week 1
**[[Useful Modelsim Commands]]
**[[Media:Modelsim_pe_user_10.0d.pdf | Modelsim Users Guide]]
*Week2
** [[Media:Connect_Remotely_Via_VPN.pdf | Guide to Remote Connecting]]
*Week3
**[[Adding VHDL Files to a Project]] Additions and alterations
**Hosted the scripts for Kevinss tutorial and provided a link for it
**Modified the landing page to Kevni't tutorial to have the pdf, and a link to the scripts
**Modified [[Tutorial: Creating a Custom Bitfile]], some details were unclear and/or left out about using your newly built bitfile
*Week 4
**Added a topic to the FAQ page regarding how you can use the /tmp/ directory in order to speed up certain activities such as building a bitfile or simulation. Added [[Media:UseTmpScript.sh‎ | this script]] to help with migration.

=== Osama ===
*Week 1: Creating Team Cyc05 page.
*Week 2:
**Updating [[Connecting to convey-1.ece.iastate.edu]] with usage policy
**Adding [[Frequently Asked Questions]] page
* Week 3:
**Updating the [[Frequently Asked Questions]] page
**Adding and maintaining the [[Using the Memory Controller Interface]] page
* Week 4:
**[[Media:Vhd2v isnt.txt|Python script to generate instantiation code of VHDL module in Verilog]]
**[[Media:Convey_mc_ports.txt|Python script to generate the MC interface signals in VHDL]]
**[[Media:convey_mc_ports_vhdl.txt|MC interface signals]] in VHDL
**Adding more stuff to the [[Frequently Asked Questions]] page

=== PengQing ===
*Week 1:
**[http://sn0v.wordpress.com/2012/12/07/installing-cuda-5-on-ubuntu-12-04/ Installing CUDA on Ubuntu]
**[http://graphics.stanford.edu/~mhouston/public_talks/R520-mhouston.pdf General Purpose Computation on GPUs (GPGPU)]
*Week 2:
**[http://vol.verilog.com/VOL/main.htm Verilog self-study online course]
*Week 3:
**[http://www.ece.msstate.edu/~reese/EE4743/lectures/verilog_intro_2002/verilog_intro_2002.pdf Verilog vs. VHDL]
*Week 4:
**[http://www.vogella.com/articles/Git/article.html git tutorial]

Frequently Asked Questions

2013-02-12T23:03:56Z

Tyler07: /* Why is Simulation/building bit file/ (insert here) so slow? */

== General FAQ ==
===Why is Simulation/building bit file/ (insert here) so slow?===
If you are using the the cyfiles drive to do your work, these activities all seem to run much slower. The reason is that the cyfiles is a network mapped drive, so all reads/writes will have to traverse the network. To get around this, you can use the /tmp/ directory. You can copy your project to a directory, such as /tmp/.[username]/[projectfile]. The tmp directories are occasionally cleaned out, so do not leave unsaved work there. [[Media:UseTmpScript.sh | Here‎]] is a script that will copy a give folder the the path of /tmp/.[username]/[name of folder]. The script will check to see if there is already a directory there with the same name, and if so it will alert the user. If not it will just copy the directory. *IMPORTANT* Ensure to make a copy of any changes back into your actual working directory, since the /tmp/ directory is routinely cleaned up.

=== How to start my own custom personality project? ===
Use the '''cnyScript''' as described in this tutorial: [[Convey PDK Tutorial]]

=== How to add new verilog files or directories to a PDK project? ===
By default, the PDK looks like the project/verilog directory and compiles all .v files found there. To add other Verilog directories, use this makefile variable:
<br /><nowiki>USER_VERILOG_DIRS += ../../verilog</nowiki>

== Simulator Related ==

==== Where can I find the personality signals? ====
You can find your custom personality signals in the "sim" window in ModelSim under <code>testbench > cae_fpga0 > ae_top > core > cae_pers</code>

==== How to keep the waves I simulated? ====
After adding the signals to the wave window, make sure to click anywhere in the waves window. Then, click the save button and save the current signals as "do" file. Next time you want to show the previous signals, open ModelSim using the command:

<code>vsim &</code>

Then, in the ModelSim command-line, type:

<code>do sim/wave.do</code>

Finally, click the "open" button and open the "vsim.wlf" file in the "sim" directory of your project.

==== How to run Modelsim GUI while simulating? ====
You may run the simulation in interactive mode by adding the following line to the makefile in the sim directory:

<code>USER_SIM_OPTIONS = -gui</code>

Another option is to edit the test bench (sim/tb_user.v shown below) to dump the waveforms to a file, then run the hardware simulator via command line, and finally open up the waveform file (vsim -v ./sim/vsim.wlf). This has the benefit of dumping all the signals (if your wave.do file was missing something, you'd have to rerun the simulation).

<nowiki>`timescale 1 ns / 1 ps

module tb_user();

initial begin
// Insert user code here, such as signal dumping
// set CNY_PDK_TB_USER_VLOG variable in sim/makefile
`include "PDK_SIM_CONFIG.vh"
`ifdef AE0_PRESENT
$wlfdumpvars(5,testbench.cae_fpga0.ae_top.core.cae_pers);
`endif
`ifdef AE1_PRESENT
$wlfdumpvars(5,testbench.cae_fpga1.ae_top.core.cae_pers);
`endif
`ifdef AE2_PRESENT
$wlfdumpvars(5,testbench.cae_fpga2.ae_top.core.cae_pers);
`endif
`ifdef AE3_PRESENT
$wlfdumpvars(5,testbench.cae_fpga3.ae_top.core.cae_pers);
`endif
end

endmodule
</nowiki>

== Emulator Related ==

==== How to read AEG registers in the emulator? ====
You can use the following function:
<code>
uint64 AegRead(int aeId, int aegIdx);
</code>

==== How to read/write the memory in the emulator? ====
You can use the functions AeMemLoad and AeMemStore to read and write from/to the memory as follows:

<code>
bool AeMemLoad (int aeId, int mcId, unint64 addr, int size, bool bSigned, uint64 &data); <br />
bool AeMemStore (int aeId, int mcId, unint64 addr, int size, bool bSigned, uint64 &data);
</code>

File:UseTmpScript.sh

2013-02-12T23:01:43Z

Tyler07: Script to help use the tmp directory for faster simulation/building bitfiles/ etc

Script to help use the tmp directory for faster simulation/building bitfiles/ etc

Frequently Asked Questions

2013-02-12T22:59:11Z

Tyler07: /* General FAQ */

== General FAQ ==
===Why is Simulation/building bit file/ (insert here) so slow?===
If you are using the the cyfiles drive to do your work, these activities all seem to run much slower. The reason is that the cyfiles is a network mapped drive, so all reads/writes will have to traverse the network. To get around this, you can use the /tmp/ directory. You can copy your project to a directory, such as /tmp/.[username]/[projectfile]. The tmp directories are occasionally cleaned out, so do not leave unsaved work there. Here is a script that will copy a give folder the the path of /tmp/.[username]/[name of folder]. The script will check to see if there is already a directory there with the same name, and if so it will alert the user. If not it will just copy the directory. *IMPORTANT* Ensure to make a copy of any changes back into your actual working directory, since the /tmp/ directory is routinely cleaned up.

=== How to start my own custom personality project? ===
Use the '''cnyScript''' as described in this tutorial: [[Convey PDK Tutorial]]

=== How to add new verilog files or directories to a PDK project? ===
By default, the PDK looks like the project/verilog directory and compiles all .v files found there. To add other Verilog directories, use this makefile variable:
<br /><nowiki>USER_VERILOG_DIRS += ../../verilog</nowiki>

== Simulator Related ==

==== Where can I find the personality signals? ====
You can find your custom personality signals in the "sim" window in ModelSim under <code>testbench > cae_fpga0 > ae_top > core > cae_pers</code>

==== How to keep the waves I simulated? ====
After adding the signals to the wave window, make sure to click anywhere in the waves window. Then, click the save button and save the current signals as "do" file. Next time you want to show the previous signals, open ModelSim using the command:

<code>vsim &</code>

Then, in the ModelSim command-line, type:

<code>do sim/wave.do</code>

Finally, click the "open" button and open the "vsim.wlf" file in the "sim" directory of your project.

==== How to run Modelsim GUI while simulating? ====
You may run the simulation in interactive mode by adding the following line to the makefile in the sim directory:

<code>USER_SIM_OPTIONS = -gui</code>

Another option is to edit the test bench (sim/tb_user.v shown below) to dump the waveforms to a file, then run the hardware simulator via command line, and finally open up the waveform file (vsim -v ./sim/vsim.wlf). This has the benefit of dumping all the signals (if your wave.do file was missing something, you'd have to rerun the simulation).

<nowiki>`timescale 1 ns / 1 ps

module tb_user();

initial begin
// Insert user code here, such as signal dumping
// set CNY_PDK_TB_USER_VLOG variable in sim/makefile
`include "PDK_SIM_CONFIG.vh"
`ifdef AE0_PRESENT
$wlfdumpvars(5,testbench.cae_fpga0.ae_top.core.cae_pers);
`endif
`ifdef AE1_PRESENT
$wlfdumpvars(5,testbench.cae_fpga1.ae_top.core.cae_pers);
`endif
`ifdef AE2_PRESENT
$wlfdumpvars(5,testbench.cae_fpga2.ae_top.core.cae_pers);
`endif
`ifdef AE3_PRESENT
$wlfdumpvars(5,testbench.cae_fpga3.ae_top.core.cae_pers);
`endif
end

endmodule
</nowiki>

== Emulator Related ==

==== How to read AEG registers in the emulator? ====
You can use the following function:
<code>
uint64 AegRead(int aeId, int aegIdx);
</code>

==== How to read/write the memory in the emulator? ====
You can use the functions AeMemLoad and AeMemStore to read and write from/to the memory as follows:

<code>
bool AeMemLoad (int aeId, int mcId, unint64 addr, int size, bool bSigned, uint64 &data); <br />
bool AeMemStore (int aeId, int mcId, unint64 addr, int size, bool bSigned, uint64 &data);
</code>

Team Cyc05

2013-02-05T23:29:48Z

Tyler07: /* Weekly Presentations */

File:Cyc05 week3 presentation.pdf

2013-02-05T23:28:42Z

Tyler07: our week three presentation

our week three presentation

Tutorial: Creating a Custom Bitfile

2013-02-05T02:12:09Z

Tyler07: /* Choose a New Signature */

This page covers the creation and installation of a custom personality/bitfile (a modification of the vector adder sample project).

== Building a Bitfile ==
Copy the newest version of the [[Running the Vector Adder Example Application#Compiling the Project|example project]] and set your [[Convey environment setup|environment variables]] if you have not done so already. You can make a small modification to the verilog code if you wish, such as making it a vector subtractor instead of a vector adder.

Next, compile your bitfile:

cd ~/pdk_sample/cae_vadd/phys
make

The bitfile will take a long time to create (while the Reference Manual states 2 to 4 hours, it may take much longer). Be patient.

Next, package your bitfile using the command:

make release

After make release has finished there will be a directory on the same level as your top level project directory called:

myproject.released

Inside of that folder there will be a folder with the current date. Go to the most recent directory and there will be a file called cae_fpga.tgz, this file needs to be copied into the directory:

/myprojectname/personalities/<personality number>/

Example command:

cp cae_fpga.tgz ../../myprojectname/personalities/<personality number>/ae_fpga.tgz

Note that cae_fpga.tgz needs to be renamed to ae_fpga.tgz

Note that make and make release will NOT do this copy for you. If you forget you will still be using the old personality

=== FPGA Usage Statistics ===

The device usage statistics are displayed on the terminal while building the bitfile. The log is saved to disk at:

{project directory}/phys/cae_fpga.map
OR
{project directory}/phys/cae_fpga.par

Search the end of the log file for "Design Summay" for a percentage break down in LUT, Flip flop, and BRAM usage.

== Choose a New Signature ==
Custom personalities should not use the default PDK signature (4.1.1.1.0). Choose a new signature between 65000 and 65535. In this example, we will use 65123.1.1.1.0.

You will need to create a new directory and copy the pertinent files to this directory:

cd /opt/convey/personalities
mkdir 65123.1.1.1.0
cd 65123.1.1.1.0

cp /home/PROJECT_RELEASE/DATE/cae_fpga.tgz ./ae_fpga.tgz

This is the only required file, but you may copy PersDesc.dat from the default PDK folder to your new folder and uncomment additional custom instructions you have used.

cp /opt/convey/personalities/4.1.1.1.0/PersDesc.dat ./

Instead of adding a new directory to Convey's personality folder as done above, you may set the CNY_PERSONALITY_PATH environment variable to any directory, i.e.

export CNY_PERSONALITY_PATH=/home/PROJECT_PATH/
or
setenv CNY_PERSONALITY_PATH /home/PROJECT_PATH/

The default when the CNY_PERSONALITY_PATH is not set is to use the /opt/convey/personalities folder.

You will also need to update the ''customdb'' file in /opt/convey/personalities (or create your own customdb file in your user defined personalities folder). This file is used by the cny_get_signature function and converts strings to a signature number. Our customdb file contains the following text:

65123.1.1.1.0,subtractor

Finally, there are certain places in the code where you should ensure that the signature has been updated.

* In the simulator (/sim/CaeIsaVadd.cpp), update: '''#define PERS_SIGN_CAE 0xfe63001000101000LL''', where 0xfe63 is the hex value for your signature (65123).
* In the C code, (SampleAppVadd/UserApp.c) update: '''cny_get_signature("subtractor", &sig, &sig2, &stat);''', where "subtractor" is the pseudo name of your CAE given in the customdb file.
* In the assembly code, (SampleAppVadd/cpVadd.s) update the signature directive: '''.signature pdk=65123'''

When you change the personalities directory, flush the MP cache. This will erase the cache, which is necessary if you've updated your custom bitfile:

/opt/convey/sbin/mpcache -f

You can also add a signature, and preload a given bitfile by using the commands:

/opt/convey/sbin/mpcache -add -S<personality number>
/opt/convey/sbin/mpcache -load -S<personality number>

Additional details are available in Appendix D of the [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]].

== See Also ==
* [[Using a Custom Bitfile in C Code]]

== References ==
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] - Sections 9.4.6, 9.4.7, 10, Appendix D

Team Cyc05

2013-02-05T02:11:03Z

Tyler07: /* Wiki Contributions */

Tutorial: Creating a Custom Bitfile

2013-02-05T02:10:09Z

Tyler07: /* Building a Bitfile */

This page covers the creation and installation of a custom personality/bitfile (a modification of the vector adder sample project).

== Building a Bitfile ==
Copy the newest version of the [[Running the Vector Adder Example Application#Compiling the Project|example project]] and set your [[Convey environment setup|environment variables]] if you have not done so already. You can make a small modification to the verilog code if you wish, such as making it a vector subtractor instead of a vector adder.

Next, compile your bitfile:

cd ~/pdk_sample/cae_vadd/phys
make

The bitfile will take a long time to create (while the Reference Manual states 2 to 4 hours, it may take much longer). Be patient.

Next, package your bitfile using the command:

make release

After make release has finished there will be a directory on the same level as your top level project directory called:

myproject.released

Inside of that folder there will be a folder with the current date. Go to the most recent directory and there will be a file called cae_fpga.tgz, this file needs to be copied into the directory:

/myprojectname/personalities/<personality number>/

Example command:

cp cae_fpga.tgz ../../myprojectname/personalities/<personality number>/ae_fpga.tgz

Note that cae_fpga.tgz needs to be renamed to ae_fpga.tgz

Note that make and make release will NOT do this copy for you. If you forget you will still be using the old personality

=== FPGA Usage Statistics ===

The device usage statistics are displayed on the terminal while building the bitfile. The log is saved to disk at:

{project directory}/phys/cae_fpga.map
OR
{project directory}/phys/cae_fpga.par

Search the end of the log file for "Design Summay" for a percentage break down in LUT, Flip flop, and BRAM usage.

== Choose a New Signature ==
Custom personalities should not use the default PDK signature (4.1.1.1.0). Choose a new signature between 65000 and 65535. In this example, we will use 65123.1.1.1.0.

You will need to create a new directory and copy the pertinent files to this directory:

cd /opt/convey/personalities
mkdir 65123.1.1.1.0
cd 65123.1.1.1.0

cp /home/PROJECT_RELEASE/DATE/cae_fpga.tgz ./ae_fpga.tgz

This is the only required file, but you may copy PersDesc.dat from the default PDK folder to your new folder and uncomment additional custom instructions you have used.

cp /opt/convey/personalities/4.1.1.1.0/PersDesc.dat ./

Instead of adding a new directory to Convey's personality folder as done above, you may set the CNY_PERSONALITY_PATH environment variable to any directory, i.e.

export CNY_PERSONALITY_PATH=/home/PROJECT_PATH/
or
setenv CNY_PERSONALITY_PATH /home/PROJECT_PATH/

The default when the CNY_PERSONALITY_PATH is not set is to use the /opt/convey/personalities folder.

You will also need to update the ''customdb'' file in /opt/convey/personalities (or create your own customdb file in your user defined personalities folder). This file is used by the cny_get_signature function and converts strings to a signature number. Our customdb file contains the following text:

65123.1.1.1.0,subtractor

Finally, there are certain places in the code where you should ensure that the signature has been updated.

* In the simulator (/sim/CaeIsaVadd.cpp), update: '''#define PERS_SIGN_CAE 0xfe63001000101000LL''', where 0xfe63 is the hex value for your signature (65123).
* In the C code, (SampleAppVadd/UserApp.c) update: '''cny_get_signature("subtractor", &sig, &sig2, &stat);''', where "subtractor" is the pseudo name of your CAE given in the customdb file.
* In the assembly code, (SampleAppVadd/cpVadd.s) update the signature directive: '''.signature pdk=65123'''

When you change the personalities directory, flush the MP cache. This will erase the cache, which is necessary if you've updated your custom bitfile:

/opt/convey/sbin/mpcache -f

You can also add a signature, and preload a given bitfile by using the commands:

/opt/convey/sbin/mpcache -add -S<personality>
/opt/convey/sbin/mpcache -load -S<personality>

Additional details are available in Appendix D of the [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]].

== See Also ==
* [[Using a Custom Bitfile in C Code]]

== References ==
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] - Sections 9.4.6, 9.4.7, 10, Appendix D

Team Cyc05

2013-02-02T22:42:59Z

Tyler07: /* Wiki Contributions */

Adding VHDL Files to a Project

2013-02-02T22:38:59Z

Tyler07: /* Using Your VHDL Module In The Top Level cae_pers.v File */

== Using Your VHDL Module In The Top Level cae_pers.v File==
=== Entity Definition ===

entity test is
port(
in1 : in std_logic;
in2 : in std_logic;
out1: out std_logic);
end entity;

=== Instantiation in Verilog ===

*It will look exactly like any other module instantiation in verilog.
test t1(
.in1(myInput),
.in2(myOtherInput),
.out(myOutput)
);
=== Module With Vectors ===
*If we change the earlier definition to look like the following
entity testWithVector is
port(
in1 : in std_logic_vector(63 downto 0);
in2 : in std_logic_vector(63 downto 0);
out1: out std_logic);
end entity;
*Notice that the expected input is a 64 bit wide signal path
*Assume that you have a Verilog reg as follows
reg [63:0] myReg;
reg [63:0] myOtherReg;
*Modlesim will let you directly map myReg to in1 or in2 (see below), however ISE will generally fail to compile this code, with an error about the expected size being incorrect
test t1(
.in1(myReg),
.in2(myOtherReg),
.out(myOutput)
);
*The easiest way around this is to map myReg to a wire, and use that in the instantiation of your VHDL module
wire [63:0] wire_myReg;
wire [63:0] wire_myOtherReg;
assign wire_myReg = myReg;
assign wire_myOtherReg = myOtherReg;

test t1(
.in1(wire_myReg),
.in2(wire_myOtherReg),
.out(myOutput)
);

== Include Option 1 ==
Use the USER_VHDL_FILES variable in the project makefile:

USER_VHDL_FILES += file1.vhd file2.vhd

The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled.

== Include Option 1.1 ==
Use the USER_VHDL_FILES variable in the project's top level Makefile.include:
USER_VHDL_FILES += ../vhdl/file.vhd
*Still use the ../ because this path will get included in the lower level directories, and the makefile there will still expect a relative path.

== Include Option 2 ==
Create site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile:

CNY_PDK_USER_DIRECTORY
CNY_PDK_SITE_DIRECTORY

This is a good place to set which simulator you use, set up signal tracing, etc.

== Other information ==
There are also several variables in the makefile that allow you to create dependencies for your own make flow. For example, the variable USER_SIM_DEPENDENCIES is listed as a dependency for the simulation, so if you want to run your own compile step before running the simulation, you can set that variable and the dependency will cause it to run that step at the right time. Others are USER_COMPILE_DEPENDENCIES and USER_PHYS_DEPENDENCIES, which is a dependency of the synthesis target.

Adding VHDL Files to a Project

2013-02-02T22:24:11Z

Tyler07:

== Using Your VHDL Module In The Top Level cae_pers.v File==

== Include Option 1 ==
Use the USER_VHDL_FILES variable in the project makefile:

USER_VHDL_FILES += file1.vhd file2.vhd

The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled.

== Include Option 1.1 ==
Use the USER_VHDL_FILES variable in the project's top level Makefile.include:
USER_VHDL_FILES += ../vhdl/file.vhd
*Still use the ../ because this path will get included in the lower level directories, and the makefile there will still expect a relative path.

== Include Option 2 ==
Create site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile:

CNY_PDK_USER_DIRECTORY
CNY_PDK_SITE_DIRECTORY

This is a good place to set which simulator you use, set up signal tracing, etc.

== Other information ==
There are also several variables in the makefile that allow you to create dependencies for your own make flow. For example, the variable USER_SIM_DEPENDENCIES is listed as a dependency for the simulation, so if you want to run your own compile step before running the simulation, you can set that variable and the dependency will cause it to run that step at the right time. Others are USER_COMPILE_DEPENDENCIES and USER_PHYS_DEPENDENCIES, which is a dependency of the synthesis target.

Adding VHDL Files to a Project

2013-02-02T22:20:42Z

Tyler07: /* Option 1 */

== Option 1 ==
Use the USER_VHDL_FILES variable in the project makefile:

USER_VHDL_FILES += file1.vhd file2.vhd

The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled.

== Option 1.1 ==
Use the USER_VHDL_FILES variable in the project's top level Makefile.include:
USER_VHDL_FILES += ../vhdl/file.vhd
*Still use the ../ because this path will get included in the lower level directories, and will still expect a relative path.

== Option 2 ==
Create site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile:

CNY_PDK_USER_DIRECTORY
CNY_PDK_SITE_DIRECTORY

This is a good place to set which simulator you use, set up signal tracing, etc.

== Other information ==
There are also several variables in the makefile that allow you to create dependencies for your own make flow. For example, the variable USER_SIM_DEPENDENCIES is listed as a dependency for the simulation, so if you want to run your own compile step before running the simulation, you can set that variable and the dependency will cause it to run that step at the right time. Others are USER_COMPILE_DEPENDENCIES and USER_PHYS_DEPENDENCIES, which is a dependency of the synthesis target.

Main Page

2013-01-30T02:18:02Z

Tyler07: /* Convey HC-1 Tutorials */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Running the Vector Adder Example Application]]
* [[Convey PDK Tutorial]]

* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]
* [[Using the Write-Complete Interface]]
* [[Using the Timing Analyzer]]

* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]
* [[Frequently Asked Questions]]

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://www.asic-world.com www.asic-world.com] - Great Tutorials for those Learning HDLs
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://www.c7t-hdl.com/Docs/C7T_AN05_Customized_WaveView_ModelSim_ISE.pdf Modelsim and ISE]
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]
* [[Media:Modelsim_pe_user_10.0d.pdf | Modelsim Users Guide]]
* [[Useful Modelsim Commands]]
* [http://sn0v.wordpress.com/2012/12/07/installing-cuda-5-on-ubuntu-12-04/ Installing CUDA on Ubuntu]
* [http://graphics.stanford.edu/~mhouston/public_talks/R520-mhouston.pdf General Purpose Computation on GPUs (GPGPU)]
* Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]
* [[Media:Connect_Remotely_Via_VPN.pdf | Guide to Remote Connecting]]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]
== Spring 2013 Teams ==
* [[Team Cyc05]]
* [[Team Challenger]]
* [[Team Blitz]]

Convey PDK Tutorial

2013-01-30T02:17:13Z

Tyler07: /* Convey PDK Tutorial */

[[Media:ConveyTutorial1.pdf | Tutorial PDF]]

[http://www.public.iastate.edu/~tyler07/cnyScripts.tar.gz Required Scripts]

Convey PDK Tutorial

2013-01-30T02:16:38Z

Tyler07:

==Convey PDK Tutorial==
[[Media:ConveyTutorial1.pdf | Tutorial PDF]]

[http://www.public.iastate.edu/~tyler07/cnyScripts.tar.gz Required Scripts]

Convey PDK Tutorial

2013-01-30T01:55:36Z

Tyler07: New page: Tutorial PDF Scripts Directory

[[image:ConveyTutorial1.pdf | Tutorial PDF]]
[[medial: | Scripts Directory]]

Main Page

2013-01-30T01:55:04Z

Tyler07: /* Convey HC-1 Tutorials */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Running the Vector Adder Example Application]]
* [[Convey PDK Tutorial]]
* Convey pdk tutorial: [[image:ConveyTutorial1.pdf]] (uses newCnyProject script)
* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]
* [[Using the Write-Complete Interface]]
* [[Using the Timing Analyzer]]

* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]
* [[Frequently Asked Questions]]

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://www.asic-world.com www.asic-world.com] - Great Tutorials for those Learning HDLs
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://www.c7t-hdl.com/Docs/C7T_AN05_Customized_WaveView_ModelSim_ISE.pdf Modelsim and ISE]
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]
* [[Media:Modelsim_pe_user_10.0d.pdf | Modelsim Users Guide]]
* [[Useful Modelsim Commands]]
* [http://sn0v.wordpress.com/2012/12/07/installing-cuda-5-on-ubuntu-12-04/ Installing CUDA on Ubuntu]
* [http://graphics.stanford.edu/~mhouston/public_talks/R520-mhouston.pdf General Purpose Computation on GPUs (GPGPU)]
* Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]
* [[Media:Connect_Remotely_Via_VPN.pdf | Guide to Remote Connecting]]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]
== Spring 2013 Teams ==
* [[Team Cyc05]]
* [[Team Challenger]]
* [[Team Blitz]]

Team Cyc05

2013-01-29T21:30:58Z

Tyler07: /* Wiki Contributions */

Team Cyc05

2013-01-29T21:30:27Z

Tyler07: /* Weekly Presentations */

File:Cyc05 Week 2.pdf

2013-01-29T21:29:13Z

Tyler07:

Team Cyc05

2013-01-29T21:27:04Z

Tyler07: /* Weekly Presentations */

Team Cyc05

2013-01-29T21:26:45Z

Tyler07: /* Weekly Presentations */

Team Cyc05

2013-01-29T21:26:33Z

Tyler07:

Team Cyc05

2013-01-29T19:58:26Z

Tyler07: /* Wiki Contributions */

Team Cyc05

2013-01-29T19:58:11Z

Tyler07: /* Wiki Contributions */

Main Page

2013-01-29T19:57:35Z

Tyler07: /* Helpful Guides */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Running the Vector Adder Example Application]]
* Convey pdk tutorial: [[image:ConveyTutorial1.pdf]] (uses newCnyProject script)
* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]
* [[Using the Write-Complete Interface]]
* [[Using the Timing Analyzer]]

* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://www.asic-world.com www.asic-world.com] - Great Tutorials for those Learning HDLs
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://www.c7t-hdl.com/Docs/C7T_AN05_Customized_WaveView_ModelSim_ISE.pdf Modelsim and ISE]
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]
* [[Media:Modelsim_pe_user_10.0d.pdf | Modelsim Users Guide]]
* [[Useful Modelsim Commands]]
* [http://sn0v.wordpress.com/2012/12/07/installing-cuda-5-on-ubuntu-12-04/ Installing CUDA on Ubuntu]
* [http://graphics.stanford.edu/~mhouston/public_talks/R520-mhouston.pdf General Purpose Computation on GPUs (GPGPU)]
* Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]
* [[Media:Connect_Remotely_Via_VPN.pdf | Guide to Remote Connecting]]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]
== Spring 2013 Teams ==
* [[Team Cyc05]]
* [[Team Challenger]]
* [[Team Blitz]]

File:Connect Remotely Via VPN.pdf

2013-01-29T19:56:19Z

Tyler07: Guide to remote connect

Guide to remote connect

Team Cyc05

2013-01-21T19:56:34Z

Tyler07: /* Wiki Contributions */

Team Cyc05

2013-01-21T19:55:48Z

Tyler07:

Main Page

2013-01-21T19:53:04Z

Tyler07: /* Helpful Guides */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Running the Vector Adder Example Application]]
* Convey pdk tutorial: [[image:ConveyTutorial1.pdf]] (uses newCnyProject script)
* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]
* [[Using the Write-Complete Interface]]
* [[Using the Timing Analyzer]]

* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://www.asic-world.com www.asic-world.com] - Great Tutorials for those Learning HDLs
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://www.c7t-hdl.com/Docs/C7T_AN05_Customized_WaveView_ModelSim_ISE.pdf Modelsim and ISE]
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]
* [[Media:Modelsim_pe_user_10.0d.pdf | Modelsim Users Guide]]
* [[Useful Modelsim Commands]]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]
== Spring 2013 Teams ==
* [[Team Cyc05]]
* [[Team Challenger]]

File:Modelsim pe user 10.0d.pdf

2013-01-21T19:48:13Z

Tyler07: Modelsim users manual v10.0

Modelsim users manual v10.0

Main Page

2013-01-21T19:45:22Z

Tyler07: /* Helpful Guides */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Running the Vector Adder Example Application]]
* Convey pdk tutorial: [[image:ConveyTutorial1.pdf]] (uses newCnyProject script)
* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]
* [[Using the Write-Complete Interface]]
* [[Using the Timing Analyzer]]

* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://www.asic-world.com www.asic-world.com] - Great Tutorials for those Learning HDLs
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://www.c7t-hdl.com/Docs/C7T_AN05_Customized_WaveView_ModelSim_ISE.pdf Modelsim and ISE]
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]
* [[Modelsim Users Manual]]
* [[Useful Modelsim Commands]]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]
== Spring 2013 Teams ==
* [[Team Cyc05]]
* [[Team Challenger]]

Useful Modelsim Commands

2013-01-21T19:41:20Z

Tyler07: /* Useful Modelsim Commands */

== Useful Modelsim Commands ==
Restart A Simulation
restart -f

Save a waveform to a .wlf file
dataset save [dataset] [output file]

You can also start vsim with the -wlf flag, which will automatically save the waveform to a .wlf file.
However, doing the save from the command line after the simulation has been run, will be safer in terms of overwriting old .wlf files you may want to keep around.

List the available datasets
dataset list

Run the whole test bench
run -all

Run the simulation for n amount of time
run [n][unit] e.x. run 100us

Useful Modelsim Commands

2013-01-21T19:41:01Z

Tyler07: New page: == Useful Modelsim Commands == Restart A Simulation restart -f Save a waveform to a .wlf file dataset save [dataset] [output file] You can also start vsim with the -wlf flag, which wi...

== Useful Modelsim Commands ==
Restart A Simulation
restart -f

Save a waveform to a .wlf file
dataset save [dataset] [output file]

You can also start vsim with the -wlf flag, which will automatically save the waveform to a .wlf file.
However, doing the save from the command line after the simulation has been run will be safer in terms of overwriting old .wlf files you may want to keep around.

List the available datasets
dataset list

Run the whole test bench
run -all

Run the simulation for n amount of time
run [n][unit] e.x. run 100us

Main Page

2013-01-21T19:33:37Z

Tyler07: /* Helpful Guides */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Running the Vector Adder Example Application]]
* Convey pdk tutorial: [[image:ConveyTutorial1.pdf]] (uses newCnyProject script)
* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]
* [[Using the Write-Complete Interface]]
* [[Using the Timing Analyzer]]

* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://www.asic-world.com www.asic-world.com] - Great Tutorials for those Learning HDLs
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://www.c7t-hdl.com/Docs/C7T_AN05_Customized_WaveView_ModelSim_ISE.pdf Modelsim and ISE]
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]
* [[Useful Modelsim Commands]]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]
== Spring 2013 Teams ==
* [[Team Cyc05]]
* [[Team Challenger]]

Running the Vector Adder Example Application

2013-01-21T19:08:46Z

Tyler07: It wasn't clear to me which makefile to edit, so I specifically noted which one to edit for the USER_SIM_OPTIONS = -gui

Section 10.5 of the [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] explains how to run the sample software application. It has been reproduced below in brief.

== Compiling the Project ==
The rev version installed on the Convey machine is from 2012-03-19; to copy the sample app's source code run:
cd ~
mkdir pdk_sample
cp -r /opt/convey/pdk/latest/hc-1/examples/* pdk_sample

To make the sample project, first make sure you have [[Convey environment setup|setup your environment variables]], then run:

cd ~/pdk_sample/cae_pers_vadd/SampleAppVadd/
make

This compiles both an emulator (CaeSimPers) and a C program that makes a coprocessor call to use the vector adder (UserApp.exe).

== Run the Project ==
There are three ways to run your project:
# A software simulation of the FPGA design
# A hardware simulation (ModelSim) of the FPGA design
# The actual implementation (C code, Verilog code). The bitfile was previously compiled, nicknamed, and added to a known file location (/opt/convey/personalties/...).

There are some scripts that can be used to run the various projects.

The '''runcp''' (i.e. run coprocessor) script located in the SampleAppVadd can be used to run the application in HW which sets the appropriate environment variables and runs the UserApp.exe:

./runcp

The '''run''' script located in the SampleAppVadd can be used to run the application using the software simulation of the FPGA design.

./run

Using the "-vsim" option, either script can be used to run the application using the hardware simulation (ModelSim). The "-vsim" option sets the environment variable CNY_CAE_EMULATOR to ./run_simulation:

./runcp -vsim
or
./run -vsim

To summarize the important environment variables:

{| border="1" cellpadding="5" cellspacing="0"
|-
|'''Environment Variables''' || '''Software''' || '''ModelSim''' || '''Hardware'''
|-
|CNY_SIM_THREAD || libcpSimLib2.so || libcpSimLib2.so || ''unset''
|-
|CNY_CAE_EMULATOR || <location for CaeSimPers> || ./run_simulation || ''unset''
|}

=== Interactive Mode for ModelSim Simulation ===
Source: http://www.conveysupport.com/help/?p=215

You can save the waveforms every time you run the hardware simulator to make debugging easier.

Add the $wlfdumpvars line to the sim/tb_user.v file:
// To trace everything (slow)
$wlfdumpvars(0, testbench);
// To trace cae_pers module and 5 levels below
`ifdef AE0_PRESENT
$wlfdumpvars(5,testbench.cae_fpga0.ae_top.core.cae_pers);

Then include that file in the sim/Makefile by adding this line this line:
CNY_PDK_TB_USER_VLOG += ./tb_user.v

This will create a vsim.wlf file in the sim directory. You can view the waveform using any of the following terminal commands:
vsim ../sim/vsim.wlf
vsim -view ../sim/vsim.wlf

Alternatively, you may instead run the simulation in interactive mode by adding the following line to the makefile in the sim directory:
USER_SIM_OPTIONS = -gui
Then run the app (./run -vsim) to start the simulation. When the Modelsim GUI opens and the design is loaded, type “run -all” at the Modelsim command line.

Team Cyc05

2013-01-17T00:19:14Z

Tyler07:

Team Cyc05

2013-01-16T22:10:43Z

Tyler07: