== Using Your VHDL Module In The Top Level cae_pers.v File==
=== Entity Definition ===

entity test is
port(
in1 : in std_logic;
in2 : in std_logic;
out1: out std_logic);
end entity;

=== Instantiation in Verilog ===

*It will look exactly like any other module instantiation in Verilog.
<code> test t1(
.in1(myInput),
.in2(myOtherInput),
.out(myOutput)
);</code>

*Another easier way is to use this [[Media:Vhd2v isnt.txt|Python script]] to generate instantiation code in Verilog. Use the following command:
<code> source cny_Env
$ mv ./vhd2v_inst.txt /.vhd2v_isnt.py
$ ./vhd2v_inst.py <filename></code>

=== Module With Vectors ===
*If we change the earlier definition to look like the following
entity testWithVector is
port(
in1 : in std_logic_vector(63 downto 0);
in2 : in std_logic_vector(63 downto 0);
out1: out std_logic);
end entity;
*Notice that the expected input is a 64 bit wide signal path
*Assume that you have a Verilog reg as follows
reg [63:0] myReg;
reg [63:0] myOtherReg;
*Modlesim will let you directly map myReg to in1 or in2 (see below), however ISE will generally fail to compile this code, with an error about the expected size being incorrect
test t1(
.in1(myReg),
.in2(myOtherReg),
.out(myOutput)
);
*The easiest way around this is to map myReg to a wire, and use that in the instantiation of your VHDL module
wire [63:0] wire_myReg;
wire [63:0] wire_myOtherReg;
assign wire_myReg = myReg;
assign wire_myOtherReg = myOtherReg;

test t1(
.in1(wire_myReg),
.in2(wire_myOtherReg),
.out(myOutput)
);

== Include Option 1 ==
Use the USER_VHDL_FILES variable in the project makefile:

USER_VHDL_FILES += file1.vhd file2.vhd

The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled.

== Include Option 1.1 ==
Use the USER_VHDL_FILES variable in the project's top level Makefile.include:
USER_VHDL_FILES += ../vhdl/file.vhd
*Still use the ../ because this path will get included in the lower level directories, and the makefile there will still expect a relative path.

== Include Option 2 ==
Create site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile:

CNY_PDK_USER_DIRECTORY
CNY_PDK_SITE_DIRECTORY

This is a good place to set which simulator you use, set up signal tracing, etc.

== Other information ==
There are also several variables in the makefile that allow you to create dependencies for your own make flow. For example, the variable USER_SIM_DEPENDENCIES is listed as a dependency for the simulation, so if you want to run your own compile step before running the simulation, you can set that variable and the dependency will cause it to run that step at the right time. Others are USER_COMPILE_DEPENDENCIES and USER_PHYS_DEPENDENCIES, which is a dependency of the synthesis target.

File:Cyc05 week4 presentation.pdf

2013-02-12T23:27:30Z

Ogamal: uploaded a new version of "Image:Cyc05 week4 presentation.pdf"

Team Cyc05

2013-02-12T23:19:48Z

Ogamal: /* Weekly Presentations */

{| border="1" cellpadding="5" cellspacing="0" align="right"
|+'''Team Cyc05'''
|-
| align="center" width="200px" | [[Image:Cy.jpg]]
|-
! style="background:#CD1014;" | Cyc05 Team Logo
|-
|-
| colspan="2" align="center" |
{| border="0"
|+''Team Members''
|-
| Osama G. Attia (ogamal)
|-
| Tyler Johnson (tyler07)
|-
| PengQing Xie (carterp)
|}
|}

== Team Members ==
* Osama G. Attia
* Tyler Johnson
* PengQing Xie

== Weekly Presentations ==
*Week 1 - [[Media:Cyc05_-_Presentation_01.pdf | Presentation Slides Week 1]]
*Week 2 - [[Media:Cyc05_Week_2.pdf | Presentation Slides Week 2]]
*Week 3 - [[Media:Cyc05_week3_presentation.pdf‎ | Presentation Slides Week 3]]
*Week 4 - [[Media:Cyc05_week4_presentation.pdf‎ | Presentation Slides Week 4]]

== Wiki Contributions ==
=== Tyler ===
*Week 1
**[[Useful Modelsim Commands]]
**[[Media:Modelsim_pe_user_10.0d.pdf | Modelsim Users Guide]]
*Week2
** [[Media:Connect_Remotely_Via_VPN.pdf | Guide to Remote Connecting]]
*Week3
**[[Adding VHDL Files to a Project]] Additions and alterations
**Hosted the scripts for Kevinss tutorial and provided a link for it
**Modified the landing page to Kevni't tutorial to have the pdf, and a link to the scripts
**Modified [[Tutorial: Creating a Custom Bitfile]], some details were unclear and/or left out about using your newly built bitfile
*Week 4
**Added a topic to the FAQ page regarding how you can use the /tmp/ directory in order to speed up certain activities such as building a bitfile or simulation. Added [[Media:UseTmpScript.sh‎ | this script]] to help with migration.

=== Osama ===
*Week 1: Creating Team Cyc05 page.
*Week 2:
**Updating [[Connecting to convey-1.ece.iastate.edu]] with usage policy
**Adding [[Frequently Asked Questions]] page
* Week 3:
**Updating the [[Frequently Asked Questions]] page
**Adding and maintaining the [[Using the Memory Controller Interface]] page
* Week 4:
**[[Media:Vhd2v isnt.txt|Python script to generate instantiation code of VHDL module in Verilog]]
**[[Media:Convey_mc_ports.txt|Python script to generate the MC interface signals in VHDL]]
**[[Media:convey_mc_ports_vhdl.txt|MC interface signals]] in VHDL
**Adding more stuff to the [[Frequently Asked Questions]] page

=== PengQing ===
*Week 1:
**[http://sn0v.wordpress.com/2012/12/07/installing-cuda-5-on-ubuntu-12-04/ Installing CUDA on Ubuntu]
**[http://graphics.stanford.edu/~mhouston/public_talks/R520-mhouston.pdf General Purpose Computation on GPUs (GPGPU)]
*Week 2:
**[http://vol.verilog.com/VOL/main.htm Verilog self-study online course]
*Week 3:
**[http://www.ece.msstate.edu/~reese/EE4743/lectures/verilog_intro_2002/verilog_intro_2002.pdf Verilog vs. VHDL]
*Week 4:
**[http://www.vogella.com/articles/Git/article.html git tutorial]

Using the Memory Controller Interface

2013-02-05T23:59:19Z

Ogamal: /* Reading from Memory */

== Memory Controller Interface functionality ==
* Each of the Convey application engines are connected to 8 MCs (Memory Controllers) through 300MHz DDR interface.
* Each of the 8 MC interfaces consists of two 150MHz ports (odd port and even port). So, the MC interface contains a total of 16 port.
* The data from the two even and odd ports are multiplexed onto the same 300 MHz channel in the MC interface.
* Each of the even and odd ports has its request signals and response signals.
* Refer to section 9.3.3.1 in the PDK reference manual for further informations.

== Memory Controller Interface Signals ==
The 4th MC interface of the 8 MC interfaces has the signals shown in the table below. There exist MC interfaces for n = 0 to 7. Also, you can notice that the signals are the same for the even and odd port. However, the signals for the even port use the suffix <code>_e</code> and the signals for the odd port use the suffix <code>_o</code>
{| border="1" class="wikitable" style="border-collapse:collapse;"
|-
! Even Port || Odd Port
|-
| mc4_req_ld_e || mc4_req_ld_o
|-
| mc4_req_st_e || mc4_req_st_o
|-
| mc4_req_size_e<1:0> || mc4_req_size_o<1:0>
|-
| mc4_req_vadr_e<47:0> || mc4_req_vadr_o<47:0>
|-
| mc4_req_wrd_rdctl_e<63:0> || mc4_req_wrd_rdctl_o<63:0>
|-
| mc4_req_flush_e || mc4_req_flush_o
|-
| mc4_rd_rq_stall_e || mc4_rd_rq_stall_o
|-
| mc4_wr_rq_stall_e || mc4_wr_rq_stall_o
|-
| mc4_rsp_push_e || mc4_rsp_push_o
|-
| mc4_rsp_stall_e || mc4_rsp_stall_o
|-
| mc4_rsp_data_e<63:0> || mc4_rsp_data_o<63:0>
|-
| mc4_rsp_rdctl_e<31:0> || mc4_rsp_rdctl_o<31:0>
|-
| mc4_rsp_flush_cmplt_e || mc4_rsp_flush_cmplt_o
|}

== Reading from Memory ==
* Before requesting any read from the memory, you have to make sure that <code>'''mc'''''i''_rd_rq_stall_* = '0'</code>, where <code>i</code> is the MC interface port number (could be from 0 to 7).
* To request a read from memory, you have to assert the signal <code>'''mc'''''i''_req_ld_*</code> and put the address of the data you want to read on the port <code>'''mc'''''i''_req_vadr_*</code>.
* The <code>'''mc'''''i''_req_size_*<1:0></code> is used to indicate if you want to read a byte, word, double-word or quad-word (i.e. 0x0 for byte, and 0x3 for quad-word).
* You can get requested data from the <code>'''mc'''''i''_rsp_data_*<63:0></code> bus when the signal <code>'''mc'''''i''_rsp_push_*</code> is asserted.
* The lower 31 bits of <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code> will be returned as <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code>. You should set it while requesting a read and check it in the response to identify your request.

== Writing to Memory ==
* Before requesting any write to the memory, you have to make sure that <code>'''mc'''''i''_wr_rq_stall_* = '0'</code>.
* To request a write to memory, you have to assert the signal <code>'''mc'''''i''_req_st_*</code> and put the address of the data you want to write to on the port <code>'''mc'''''i''_req_vadr_*</code>.
* The <code>'''mc'''''i''_req_size_*<1:0></code> is used to indicate the size as in the read scenario above.
* The data you want to write should goes on <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code> bus.

== References ==
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] - Sections 9.3.3

Using the Memory Controller Interface

2013-02-05T23:57:46Z

Ogamal: /* Writing to Memory */

== Memory Controller Interface functionality ==
* Each of the Convey application engines are connected to 8 MCs (Memory Controllers) through 300MHz DDR interface.
* Each of the 8 MC interfaces consists of two 150MHz ports (odd port and even port). So, the MC interface contains a total of 16 port.
* The data from the two even and odd ports are multiplexed onto the same 300 MHz channel in the MC interface.
* Each of the even and odd ports has its request signals and response signals.
* Refer to section 9.3.3.1 in the PDK reference manual for further informations.

== Memory Controller Interface Signals ==
The 4th MC interface of the 8 MC interfaces has the signals shown in the table below. There exist MC interfaces for n = 0 to 7. Also, you can notice that the signals are the same for the even and odd port. However, the signals for the even port use the suffix <code>_e</code> and the signals for the odd port use the suffix <code>_o</code>
{| border="1" class="wikitable" style="border-collapse:collapse;"
|-
! Even Port || Odd Port
|-
| mc4_req_ld_e || mc4_req_ld_o
|-
| mc4_req_st_e || mc4_req_st_o
|-
| mc4_req_size_e<1:0> || mc4_req_size_o<1:0>
|-
| mc4_req_vadr_e<47:0> || mc4_req_vadr_o<47:0>
|-
| mc4_req_wrd_rdctl_e<63:0> || mc4_req_wrd_rdctl_o<63:0>
|-
| mc4_req_flush_e || mc4_req_flush_o
|-
| mc4_rd_rq_stall_e || mc4_rd_rq_stall_o
|-
| mc4_wr_rq_stall_e || mc4_wr_rq_stall_o
|-
| mc4_rsp_push_e || mc4_rsp_push_o
|-
| mc4_rsp_stall_e || mc4_rsp_stall_o
|-
| mc4_rsp_data_e<63:0> || mc4_rsp_data_o<63:0>
|-
| mc4_rsp_rdctl_e<31:0> || mc4_rsp_rdctl_o<31:0>
|-
| mc4_rsp_flush_cmplt_e || mc4_rsp_flush_cmplt_o
|}

== Reading from Memory ==
* Before requesting any read from the memory, you have to make sure that <code>'''mc'''''i''_rd_rq_stall_* = '0'</code>, where <code>i</code> is the MC interface port number (could be from 0 to 7).
* To request a read from memory, you have to assert the signal <code>'''mc'''''i''_req_ld_*</code> and put the address of the data you want to read on the port <code>'''mc'''''i''_req_vadr_*</code>.
* The <code>'''mc'''''i''_req_size_*<1:0></code> is used to indicate if you want to read a byte, word, double-word or quad-word (i.e. 0x0 for byte, and 0x3 for quad-word).
* The MC interface will respond with the data on the <code>'''mc'''''i''_rsp_data_*<63:0></code> bus.
* The lower 31 bits of <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code> will be returned as <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code>. You should set it while requesting a read and check it in the response to identify your request.

== Writing to Memory ==
* Before requesting any write to the memory, you have to make sure that <code>'''mc'''''i''_wr_rq_stall_* = '0'</code>.
* To request a write to memory, you have to assert the signal <code>'''mc'''''i''_req_st_*</code> and put the address of the data you want to write to on the port <code>'''mc'''''i''_req_vadr_*</code>.
* The <code>'''mc'''''i''_req_size_*<1:0></code> is used to indicate the size as in the read scenario above.
* The data you want to write should goes on <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code> bus.

== References ==
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] - Sections 9.3.3

Using the Memory Controller Interface

2013-02-05T23:49:17Z

Ogamal:

== Memory Controller Interface functionality ==
* Each of the Convey application engines are connected to 8 MCs (Memory Controllers) through 300MHz DDR interface.
* Each of the 8 MC interfaces consists of two 150MHz ports (odd port and even port). So, the MC interface contains a total of 16 port.
* The data from the two even and odd ports are multiplexed onto the same 300 MHz channel in the MC interface.
* Each of the even and odd ports has its request signals and response signals.
* Refer to section 9.3.3.1 in the PDK reference manual for further informations.

== Memory Controller Interface Signals ==
The 4th MC interface of the 8 MC interfaces has the signals shown in the table below. There exist MC interfaces for n = 0 to 7. Also, you can notice that the signals are the same for the even and odd port. However, the signals for the even port use the suffix <code>_e</code> and the signals for the odd port use the suffix <code>_o</code>
{| border="1" class="wikitable" style="border-collapse:collapse;"
|-
! Even Port || Odd Port
|-
| mc4_req_ld_e || mc4_req_ld_o
|-
| mc4_req_st_e || mc4_req_st_o
|-
| mc4_req_size_e<1:0> || mc4_req_size_o<1:0>
|-
| mc4_req_vadr_e<47:0> || mc4_req_vadr_o<47:0>
|-
| mc4_req_wrd_rdctl_e<63:0> || mc4_req_wrd_rdctl_o<63:0>
|-
| mc4_req_flush_e || mc4_req_flush_o
|-
| mc4_rd_rq_stall_e || mc4_rd_rq_stall_o
|-
| mc4_wr_rq_stall_e || mc4_wr_rq_stall_o
|-
| mc4_rsp_push_e || mc4_rsp_push_o
|-
| mc4_rsp_stall_e || mc4_rsp_stall_o
|-
| mc4_rsp_data_e<63:0> || mc4_rsp_data_o<63:0>
|-
| mc4_rsp_rdctl_e<31:0> || mc4_rsp_rdctl_o<31:0>
|-
| mc4_rsp_flush_cmplt_e || mc4_rsp_flush_cmplt_o
|}

== Reading from Memory ==
* Before requesting any read from the memory, you have to make sure that <code>'''mc'''''i''_rd_rq_stall_* = '0'</code>, where <code>i</code> is the MC interface port number (could be from 0 to 7).
* To request a read from memory, you have to assert the signal <code>'''mc'''''i''_req_ld_*</code> and put the address of the data you want to read on the port <code>'''mc'''''i''_req_vadr_*</code>.
* The <code>'''mc'''''i''_req_size_*<1:0></code> is used to indicate if you want to read a byte, word, double-word or quad-word (i.e. 0x0 for byte, and 0x3 for quad-word).
* The MC interface will respond with the data on the <code>'''mc'''''i''_rsp_data_*<63:0></code> bus.
* The lower 31 bits of <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code> will be returned as <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code>. You should set it while requesting a read and check it in the response to identify your request.

== Writing to Memory ==
* Before requesting any read from the memory, you have to make sure that <code>'''mc'''''i''_wr_rq_stall_* = '0'</code>.
* To request a write to memory, you have to assert the signal <code>'''mc'''''i''_req_st_*</code> and put the address of the data you want to write to on the port <code>'''mc'''''i''_req_vadr_*</code>.
* The <code>'''mc'''''i''_req_size_*<1:0></code> is used to indicate the size as in the read scenario above.
* The data you want to write should goes on <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code> bus.

== References ==
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] - Sections 9.3.3

Using the Memory Controller Interface

2013-02-05T23:47:48Z

Ogamal: /* Memory Controller Interface functionality */

== Memory Controller Interface functionality ==
* Each of the Convey application engines are connected to 8 MCs (Memory Controllers) through 300MHz DDR interface.
* Each of the 8 MC interfaces consists of two 150MHz ports (odd port and even port). So, the MC interface contains a total of 16 port.
* The data from the two even and odd ports are multiplexed onto the same 300 MHz channel in the MC interface.
* Each of the even and odd ports has its request signals and response signals.
* Refer to section 9.3.3.1 in the PDK reference manual for further informations.

== Memory Controller Interface Signals ==
The 4th MC interface of the 8 MC interfaces has the signals shown in the table below. There exist MC interfaces for n = 0 to 7. Also, you can notice that the signals are the same for the even and odd port. However, the signals for the even port use the suffix <code>_e</code> and the signals for the odd port use the suffix <code>_o</code>
{| border="1" class="wikitable" style="border-collapse:collapse;"
|-
! Even Port || Odd Port
|-
| mc4_req_ld_e || mc4_req_ld_o
|-
| mc4_req_st_e || mc4_req_st_o
|-
| mc4_req_size_e<1:0> || mc4_req_size_o<1:0>
|-
| mc4_req_vadr_e<47:0> || mc4_req_vadr_o<47:0>
|-
| mc4_req_wrd_rdctl_e<63:0> || mc4_req_wrd_rdctl_o<63:0>
|-
| mc4_req_flush_e || mc4_req_flush_o
|-
| mc4_rd_rq_stall_e || mc4_rd_rq_stall_o
|-
| mc4_wr_rq_stall_e || mc4_wr_rq_stall_o
|-
| mc4_rsp_push_e || mc4_rsp_push_o
|-
| mc4_rsp_stall_e || mc4_rsp_stall_o
|-
| mc4_rsp_data_e<63:0> || mc4_rsp_data_o<63:0>
|-
| mc4_rsp_rdctl_e<31:0> || mc4_rsp_rdctl_o<31:0>
|-
| mc4_rsp_flush_cmplt_e || mc4_rsp_flush_cmplt_o
|}

== Reading from Memory ==
* Before requesting any read from the memory, you have to make sure that <code>'''mc'''''i''_rd_rq_stall_* = '0'</code>, where <code>i</code> is the MC interface port number (could be from 0 to 7).
* To request a read from memory, you have to assert the signal <code>'''mc'''''i''_req_ld_*</code> and put the address of the data you want to read on the port <code>'''mc'''''i''_req_vadr_*</code>.
* The <code>'''mc'''''i''_req_size_*<1:0></code> is used to indicate if you want to read a byte, word, double-word or quad-word (i.e. 0x0 for byte, and 0x3 for quad-word).
* The MC interface will respond with the data on the <code>'''mc'''''i''_rsp_data_*<63:0></code> bus.
* The lower 31 bits of <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code> will be returned as <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code>. You should set it while requesting a read and check it in the response to identify your request.

== Writing to Memory ==
* Before requesting any read from the memory, you have to make sure that <code>'''mc'''''i''_wr_rq_stall_* = '0'</code>.
* To request a write to memory, you have to assert the signal <code>'''mc'''''i''_req_st_*</code> and put the address of the data you want to write to on the port <code>'''mc'''''i''_req_vadr_*</code>.
* The <code>'''mc'''''i''_req_size_*<1:0></code> is used to indicate the size as in the read scenario above.
* The data you want to write should goes on <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code> bus.

Using the Memory Controller Interface

2013-02-05T23:45:41Z

Ogamal: /* Reading from Memory */

== Memory Controller Interface functionality ==
* Each of the Convey application engines are connected to 8 MCs (Memory Controllers) through 300MHz DDR interface.
* Each of the 8 MC interfaces consists of two 150MHz ports (odd port and even port). So, the MC interface contains a total of 16 port.
* The data from the two even and odd ports are multiplexed onto the same 300 MHz channel in the MC interface.
* Each of the even and odd ports has its request signals and response signals.
* Refer to section 9.3.3.1 in the PDK for further informations.

== Memory Controller Interface Signals ==
The 4th MC interface of the 8 MC interfaces has the signals shown in the table below. There exist MC interfaces for n = 0 to 7. Also, you can notice that the signals are the same for the even and odd port. However, the signals for the even port use the suffix <code>_e</code> and the signals for the odd port use the suffix <code>_o</code>
{| border="1" class="wikitable" style="border-collapse:collapse;"
|-
! Even Port || Odd Port
|-
| mc4_req_ld_e || mc4_req_ld_o
|-
| mc4_req_st_e || mc4_req_st_o
|-
| mc4_req_size_e<1:0> || mc4_req_size_o<1:0>
|-
| mc4_req_vadr_e<47:0> || mc4_req_vadr_o<47:0>
|-
| mc4_req_wrd_rdctl_e<63:0> || mc4_req_wrd_rdctl_o<63:0>
|-
| mc4_req_flush_e || mc4_req_flush_o
|-
| mc4_rd_rq_stall_e || mc4_rd_rq_stall_o
|-
| mc4_wr_rq_stall_e || mc4_wr_rq_stall_o
|-
| mc4_rsp_push_e || mc4_rsp_push_o
|-
| mc4_rsp_stall_e || mc4_rsp_stall_o
|-
| mc4_rsp_data_e<63:0> || mc4_rsp_data_o<63:0>
|-
| mc4_rsp_rdctl_e<31:0> || mc4_rsp_rdctl_o<31:0>
|-
| mc4_rsp_flush_cmplt_e || mc4_rsp_flush_cmplt_o
|}

== Reading from Memory ==
* Before requesting any read from the memory, you have to make sure that <code>'''mc'''''i''_rd_rq_stall_* = '0'</code>, where <code>i</code> is the MC interface port number (could be from 0 to 7).
* To request a read from memory, you have to assert the signal <code>'''mc'''''i''_req_ld_*</code> and put the address of the data you want to read on the port <code>'''mc'''''i''_req_vadr_*</code>.
* The <code>'''mc'''''i''_req_size_*<1:0></code> is used to indicate if you want to read a byte, word, double-word or quad-word (i.e. 0x0 for byte, and 0x3 for quad-word).
* The MC interface will respond with the data on the <code>'''mc'''''i''_rsp_data_*<63:0></code> bus.
* The lower 31 bits of <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code> will be returned as <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code>. You should set it while requesting a read and check it in the response to identify your request.

== Writing to Memory ==
* Before requesting any read from the memory, you have to make sure that <code>'''mc'''''i''_wr_rq_stall_* = '0'</code>.
* To request a write to memory, you have to assert the signal <code>'''mc'''''i''_req_st_*</code> and put the address of the data you want to write to on the port <code>'''mc'''''i''_req_vadr_*</code>.
* The <code>'''mc'''''i''_req_size_*<1:0></code> is used to indicate the size as in the read scenario above.
* The data you want to write should goes on <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code> bus.

Using the Memory Controller Interface

2013-02-05T23:37:35Z

Ogamal:

== Memory Controller Interface functionality ==
* Each of the Convey application engines are connected to 8 MCs (Memory Controllers) through 300MHz DDR interface.
* Each of the 8 MC interfaces consists of two 150MHz ports (odd port and even port). So, the MC interface contains a total of 16 port.
* The data from the two even and odd ports are multiplexed onto the same 300 MHz channel in the MC interface.
* Each of the even and odd ports has its request signals and response signals.
* Refer to section 9.3.3.1 in the PDK for further informations.

== Memory Controller Interface Signals ==
The 4th MC interface of the 8 MC interfaces has the signals shown in the table below. There exist MC interfaces for n = 0 to 7. Also, you can notice that the signals are the same for the even and odd port. However, the signals for the even port use the suffix <code>_e</code> and the signals for the odd port use the suffix <code>_o</code>
{| border="1" class="wikitable" style="border-collapse:collapse;"
|-
! Even Port || Odd Port
|-
| mc4_req_ld_e || mc4_req_ld_o
|-
| mc4_req_st_e || mc4_req_st_o
|-
| mc4_req_size_e<1:0> || mc4_req_size_o<1:0>
|-
| mc4_req_vadr_e<47:0> || mc4_req_vadr_o<47:0>
|-
| mc4_req_wrd_rdctl_e<63:0> || mc4_req_wrd_rdctl_o<63:0>
|-
| mc4_req_flush_e || mc4_req_flush_o
|-
| mc4_rd_rq_stall_e || mc4_rd_rq_stall_o
|-
| mc4_wr_rq_stall_e || mc4_wr_rq_stall_o
|-
| mc4_rsp_push_e || mc4_rsp_push_o
|-
| mc4_rsp_stall_e || mc4_rsp_stall_o
|-
| mc4_rsp_data_e<63:0> || mc4_rsp_data_o<63:0>
|-
| mc4_rsp_rdctl_e<31:0> || mc4_rsp_rdctl_o<31:0>
|-
| mc4_rsp_flush_cmplt_e || mc4_rsp_flush_cmplt_o
|}

== Reading from Memory ==
* Before requesting any read from the memory, you have to make sure that <code>'''mc'''''i''_rd_rq_stall_* = '0'</code>, where <code>i</code> is the MC interface port number (could be from 0 to 7).
* To request a read from memory, you have to assert the signal <code>'''mc'''''i''_req_ld_*</code> and put the address of the data you want to read on the port <code>'''mc'''''i''_req_vadr_*</code>.
* The <code>'''mc'''''i''_req_size_*<1:0></code> is used to indicate if you want to read a byte, word, double-word or quad-word (i.e. 0x0 for byte, and 0x3 for quad-word).
* The lower 31 bits of <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code> will be returned as <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code>. You should set it while requesting a read and check it in the response to identify your request.

== Writing to Memory ==
* Before requesting any read from the memory, you have to make sure that <code>'''mc'''''i''_wr_rq_stall_* = '0'</code>.
* To request a write to memory, you have to assert the signal <code>'''mc'''''i''_req_st_*</code> and put the address of the data you want to write to on the port <code>'''mc'''''i''_req_vadr_*</code>.
* The <code>'''mc'''''i''_req_size_*<1:0></code> is used to indicate the size as in the read scenario above.
* The data you want to write should goes on <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code> bus.

Team Cyc05

2013-02-05T23:28:20Z

Ogamal: /* Wiki Contributions */

{| border="1" cellpadding="5" cellspacing="0" align="right"
|+'''Team Cyc05'''
|-
| align="center" width="200px" | [[Image:Cy.jpg]]
|-
! style="background:#CD1014;" | Cyc05 Team Logo
|-
|-
| colspan="2" align="center" |
{| border="0"
|+''Team Members''
|-
| Osama G. Attia (ogamal)
|-
| Tyler Johnson (tyler07)
|-
| PengQing Xie (carterp)
|}
|}

== Team Members ==
* Osama G. Attia
* Tyler Johnson
* PengQing Xie

== Weekly Presentations ==
*Week 1 - [[Media:Cyc05_-_Presentation_01.pdf | Presentation Slides Week 1]]
*Week 2 - [[Media:Cyc05_Week_2.pdf | Presentation Slides Week 2]]

== Wiki Contributions ==
=== Tyler ===
*Week 1
**[[Useful Modelsim Commands]]
**[[Media:Modelsim_pe_user_10.0d.pdf | Modelsim Users Guide]]
*Week2
** [[Media:Connect_Remotely_Via_VPN.pdf | Guide to Remote Connecting]]
*Week3
**[[Adding VHDL Files to a Project]] Additions and alterations
**Hosted the scripts for Kevinss tutorial and provided a link for it
**Modified the landing page to Kevni't tutorial to have the pdf, and a link to the scripts
**Modified [[Tutorial: Creating a Custom Bitfile]], some details were unclear and/or left out about using your newly built bitfile

=== Osama ===
*Week 1: Creating Team Cyc05 page.
*Week 2:
**Updating [[Connecting to convey-1.ece.iastate.edu]] with usage policy.
**Adding [[Frequently Asked Questions]] page.
* Week 3:
**Updating the [[Frequently Asked Questions]] page.
**Adding and maintaining the [[Using the Memory Controller Interface]] page.

=== PengQing ===
*Week 1:
**[http://sn0v.wordpress.com/2012/12/07/installing-cuda-5-on-ubuntu-12-04/ Installing CUDA on Ubuntu]
**[http://graphics.stanford.edu/~mhouston/public_talks/R520-mhouston.pdf General Purpose Computation on GPUs (GPGPU)]
*Week 2:
**[http://vol.verilog.com/VOL/main.htm Verilog self-study online course]
**Week 3:
***[http://www.ece.msstate.edu/~reese/EE4743/lectures/verilog_intro_2002/verilog_intro_2002.pdf Verilog vs. VHDL]

Using the Memory Controller Interface

2013-02-05T23:24:45Z

Ogamal: /* Reading from Memory */

== Memory Controller Interface functionality ==
* Each of the Convey application engines are connected to 8 MCs (Memory Controllers) through 300MHz DDR interface.
* Each of the 8 MC interfaces consists of two 150MHz ports (odd port and even port). So, the MC interface contains a total of 16 port.
* The data from the two even and odd ports are multiplexed onto the same 300 MHz channel in the MC interface.
* Each of the even and odd ports has its request signals and response signals.
* Refer to section 9.3.3.1 in the PDK for further informations.

== Memory Controller Interface Signals ==
The 4th MC interface of the 8 MC interfaces has the signals shown in the table below. There exist MC interfaces for n = 0 to 7. Also, you can notice that the signals are the same for the even and odd port. However, the signals for the even port use the suffix <code>_e</code> and the signals for the odd port use the suffix <code>_o</code>
{| border="1" class="wikitable" style="border-collapse:collapse;"
|-
! Even Port || Odd Port
|-
| mc4_req_ld_e || mc4_req_ld_o
|-
| mc4_req_st_e || mc4_req_st_o
|-
| mc4_req_size_e<1:0> || mc4_req_size_o<1:0>
|-
| mc4_req_vadr_e<47:0> || mc4_req_vadr_o<47:0>
|-
| mc4_req_wrd_rdctl_e<63:0> || mc4_req_wrd_rdctl_o<63:0>
|-
| mc4_req_flush_e || mc4_req_flush_o
|-
| mc4_rd_rq_stall_e || mc4_rd_rq_stall_o
|-
| mc4_wr_rq_stall_e || mc4_wr_rq_stall_o
|-
| mc4_rsp_push_e || mc4_rsp_push_o
|-
| mc4_rsp_stall_e || mc4_rsp_stall_o
|-
| mc4_rsp_data_e<63:0> || mc4_rsp_data_o<63:0>
|-
| mc4_rsp_rdctl_e<31:0> || mc4_rsp_rdctl_o<31:0>
|-
| mc4_rsp_flush_cmplt_e || mc4_rsp_flush_cmplt_o
|}

== Reading from Memory ==
* Before requesting any read from the memory, you have to make sure that <code>'''mc'''''i''_rd_rq_stall_* = '0'</code>, where <code>i</code> is the MC interface port number (could be from 0 to 7).
* To request a read from memory, you have to assert the signal <code>'''mc'''''i''_req_ld_*</code> and put the address of the data you want to read on the port <code>'''mc'''''i''_req_vadr_*</code>.
* The <code>'''mc'''''i''_req_size_*<1:0></code> is used to indicate if you want to read a byte, word, double-word or quad-word (i.e. 0x0 for byte, and 0x3 for quad-word).
* The lower 31 bits of <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code> will be returned as <code>'''mc'''''i''_req_wrd_rdctl_*<63:0></code>. You should set it while requesting a read and check it in the response to identify your request.

== Writing to Memory ==