Cpre584 - User contributions [en]

Analyze the Simpleton Basic App

2013-02-20T01:22:50Z

Cnel711: /* Overview */

== Overview ==
Simpleton is a minimalist Convey personality that has two custom instructions. The first increments a value in an AEG register. The second uses a single memory controller to increment a value in coprocessor memory.

Advantages of using Simpleton as the start of your project include:
* It's minimalist
* It's well commented
* The top level module, personality.v, replaces cae_pers.v with awesomeness:
** The port declaration is only 50 lines and no longer scary (cae_pers.v is >150 lines)
** It wraps the memory controller interfaces in to unpacked arrays so you can easily use generate loops
** It hides unnecessary instruction decode and clock logic
** It gets rid of the CSR interface (because, honestly, you weren't going to use it anyway)
** Adds a console bell at the end of the run and runcp scripts

== Download ==
All of Chad's Convey projects are located on the RCL SVN. To checkout all projects, or just a tar.gz of simpleton:

<nowiki>
svn co svn://rcl-1.ece.iastate.edu/projects/convey/
svn co svn://rcl-1.ece.iastate.edu/projects/convey/cae_simpleton/simpleton.tar.gz</nowiki>

Open and analyze the following files, learn the directory structure, etc:

* /README
* /cae_simpleton/src/run
* /cae_simpleton/src/runcp
* /cae_simpleton/src/UserApp.c
* /cae_simpleton/src/cp.s
* /cae_simpleton/sim/CaeIsa.cpp
* /cae_simpleton/verilog/personality.v
* /cae_simpleton/coregen/README
* /cae_simpleton/phys
* /cae_simpleton/makefile.include
* /personalities/customdb
* /personalities/65100.1.1.0/

Test Benches

2013-02-20T00:56:05Z

Cnel711: New page: == Overview == Nobody likes waiting 6 minutes for Convey's hardware simulator to finish in order to see the result of a small change of code. By writing a test bench, you can be looking a...

== Overview ==
Nobody likes waiting 6 minutes for Convey's hardware simulator to finish in order to see the result of a small change of code. By writing a test bench, you can be looking at waveforms in a few seconds.

== Tutorial ==

# Open Xilinx's ISE from the terminal (make sure your [[Convey environment setup | environmental variables]] are set):
ise &
# Create or open a project. The devices on the HC-1 and HC-2 are Virtex 5 FPGAs (xc5vlx330, -2, ff1760).
# Add the DUT (DUT = device under test; i.e. the verilog file)
# Create a new testbench file (example below)
# Simulate

<nowiki>
/*
Basics of any testbench:
- create reg's for all inputs to the DUT (device under test)
- create wires for all the outputs of the DUT
- use an initial block to send the DUT stimulus

According to software, correct output of simulation
should be (seed=0, size=32, exact=1):
hash(0) = 2;
hash(10) = 12;
hash(20) = 4;
hash(30) = 19;
*/
`timescale 1ns / 1ps
module hash_tb();

reg clock, reset;
reg stall, exact_match;
reg [199:0] key;
reg [31:0] seed, table_size;
reg [1:0] control;

wire [199:0] key_out;
wire [31:0] index;
wire [1:0] control_out;

always
begin
#1 clock <= 0;
#1 clock <= 1;
end

hash dut(
// Inputs
.rst(reset),
.clk(clock),
.stall(stall),
.key(key),
.seed(seed),
.table_size(table_size),
.ctr_in(control),
.exact_match(exact_match),
// Outputs
.key_out(key_out),
.table_index(index),
.ctr_out(control_out)
);

initial
begin
reset <= 1;
stall <= 1;
key <= 0;
seed <= 0;
table_size <= 32;
control <= 3;
exact_match <= 1;

#50

reset <= 0;
stall <= 1;
key <= 0;

#100

stall <= 0;
key <= 200'h0123456789ABCDEF0123456789ABCDEF;

#100

key <= 0;

#100

key <= 10;
control <= 0;

#100

key <= 20;

#100

key <= 30;
control <= 0;

end

endmodule</nowiki>

Main Page

2013-02-20T00:49:25Z

Cnel711: /* Convey HC-1 Tutorials */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Convey PDK Tutorial]]
* [[Test Benches | Use Test Benches to test components of your Personality]]
* [[Using the Memory Controller Interface]]
* [[Running the Vector Adder Example Application]]

* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]
* [[Using the Write-Complete Interface]]
* [[Using the Timing Analyzer]]

* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]
* '''[[Frequently Asked Questions]]'''

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://www.asic-world.com www.asic-world.com] - Great Tutorials for those Learning HDLs
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://www.c7t-hdl.com/Docs/C7T_AN05_Customized_WaveView_ModelSim_ISE.pdf Modelsim and ISE]
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://www.ece.msstate.edu/~reese/EE4743/lectures/verilog_intro_2002/verilog_intro_2002.pdf Verilog vs. VHDL]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]
* [[Media:Modelsim_pe_user_10.0d.pdf | Modelsim Users Guide]]
* [[Useful Modelsim Commands]]
* [http://sn0v.wordpress.com/2012/12/07/installing-cuda-5-on-ubuntu-12-04/ Installing CUDA on Ubuntu]
* [http://graphics.stanford.edu/~mhouston/public_talks/R520-mhouston.pdf General Purpose Computation on GPUs (GPGPU)]
* Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]
* [[Media:Connect_Remotely_Via_VPN.pdf | Guide to Remote Connecting]]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2013 Teams ==
* [[Team Cyc05]]
* [[Team Challenger]]
* [[Team Blitz]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]

Analyze the Simpleton Basic App

2013-02-20T00:42:00Z

Cnel711: /* Download */

== Overview ==
Simpleton is a minimalist Convey personality that has two custom instructions. The first increments a value in an AEG register. The second uses a single memory controller to increment a value in coprocessor memory.

Advantages of using Simpleton as the start of your project include:
* It's minimalist
* It's well commented
* The top level module, personality.v is awesome:
** The port declaration is only 50 lines and no longer scary (cae_pers.v is >150 lines)
** It wraps the memory controller interfaces in to unpacked arrays so you can easily use generate loops
** It hides unnecessary instruction decode and clock logic
** It gets rid of the CSR interface (because, honestly, you weren't going to use it anyway)
** Adds a console bell at the end of the run and runcp scripts

== Download ==
All of Chad's Convey projects are located on the RCL SVN. To checkout all projects, or just a tar.gz of simpleton:

<nowiki>
svn co svn://rcl-1.ece.iastate.edu/projects/convey/
svn co svn://rcl-1.ece.iastate.edu/projects/convey/cae_simpleton/simpleton.tar.gz</nowiki>

Open and analyze the following files, learn the directory structure, etc:

* /README
* /cae_simpleton/src/run
* /cae_simpleton/src/runcp
* /cae_simpleton/src/UserApp.c
* /cae_simpleton/src/cp.s
* /cae_simpleton/sim/CaeIsa.cpp
* /cae_simpleton/verilog/personality.v
* /cae_simpleton/coregen/README
* /cae_simpleton/phys
* /cae_simpleton/makefile.include
* /personalities/customdb
* /personalities/65100.1.1.0/

Analyze the Simpleton Basic App

2013-02-20T00:33:50Z

Cnel711: /* Overview */

== Overview ==
Simpleton is a minimalist Convey personality that has two custom instructions. The first increments a value in an AEG register. The second uses a single memory controller to increment a value in coprocessor memory.

Advantages of using Simpleton as the start of your project include:
* It's minimalist
* It's well commented
* The top level module, personality.v is awesome:
** The port declaration is only 50 lines and no longer scary (cae_pers.v is >150 lines)
** It wraps the memory controller interfaces in to unpacked arrays so you can easily use generate loops
** It hides unnecessary instruction decode and clock logic
** It gets rid of the CSR interface (because, honestly, you weren't going to use it anyway)
** Adds a console bell at the end of the run and runcp scripts

== Download ==
All of Chad's Convey projects are located on the RCL SVN. To checkout:

<nowiki>
svn co svn://rcl-1.ece.iastate.edu/projects/convey/</nowiki>

Open and analyze the following files, learn the directory structure, etc:

* /README
* /cae_simpleton/src/run
* /cae_simpleton/src/runcp
* /cae_simpleton/src/UserApp.c
* /cae_simpleton/src/cp.s
* /cae_simpleton/sim/CaeIsa.cpp
* /cae_simpleton/verilog/personality.v
* /cae_simpleton/coregen/README
* /cae_simpleton/phys
* /cae_simpleton/makefile.include
* /personalities/customdb
* /personalities/65100.1.1.0/

Analyze the Simpleton Basic App

2013-02-20T00:28:31Z

Cnel711:

== Overview ==
Simpleton is a minimalist Convey personality that has two custom instructions. The first increments a value in an AEG register. The second uses a single memory controller to increment a value in coprocessor memory.

Advantages of using Simpleton as the start of your project include:
* It's minimalist
* It's well commented
* The top level module, personality.v is awesome:
** The port declaration is only 50 lines and no longer scary (cae_pers.v is >150 lines)
** It wraps the memory controller interfaces in to unpacked arrays so you can easily use generate loops
** It hides unnecessary instruction decode and clock logic
** It gets rid of the CSR interface (because, honestly, you weren't going to use it anyway)

== Download ==
All of Chad's Convey projects are located on the RCL SVN. To checkout:

<nowiki>
svn co svn://rcl-1.ece.iastate.edu/projects/convey/</nowiki>

Open and analyze the following files, learn the directory structure, etc:

* /README
* /cae_simpleton/src/run
* /cae_simpleton/src/runcp
* /cae_simpleton/src/UserApp.c
* /cae_simpleton/src/cp.s
* /cae_simpleton/sim/CaeIsa.cpp
* /cae_simpleton/verilog/personality.v
* /cae_simpleton/coregen/README
* /cae_simpleton/phys
* /cae_simpleton/makefile.include
* /personalities/customdb
* /personalities/65100.1.1.0/

Analyze the Simpleton Basic App

2013-02-20T00:14:20Z

Cnel711:

Download the simpleton app:

<nowiki>
svn co svn://rcl-1.ece.iastate.edu/projects/convey/</nowiki>

Follow the [[Running the Vector Adder Example Application | vector adder example]] for how to make and run the project.

Open and analyze the following files, learn the directory structure, etc:

* /cae_simpleton/src/run
* /cae_simpleton/src/runcp
* /cae_simpleton/src/Userapp.c
* /cae_simpleton/src/cp.s
* /cae_simpleton/sim/CaeIsa.cpp
* /cae_simpleton/verilog/personality.v
* /cae_simpleton/coregen/README
* /cae_simpleton/phys
* /cae_simpleton/makefile.include
* /personalities/customdb
* /personalities/65100.1.1.0/

Adding VHDL Files to a Project

2013-02-18T18:11:51Z

Cnel711: /* Instantiation in Verilog */

== Using Your VHDL Module In The Top Level cae_pers.v File==
=== Entity Definition ===

entity test is
port(
in1 : in std_logic;
in2 : in std_logic;
out1: out std_logic);
end entity;

=== Instantiation in Verilog ===

*It will look exactly like any other module instantiation in Verilog.
<code>test t1(
.in1(myInput),
.in2(myOtherInput),
.out(myOutput)
);</code>

*Another easier way is to use this [[Media:Vhd2v isnt.txt|Python script to generate instantiation code in Verilog]]. Use the following command:
<code>$ source cnyEnv
$ mv ./vhd2v_inst.txt /.vhd2v_isnt.py
$ ./vhd2v_inst.py <filename></code>

=== Module With Vectors ===
*If we change the earlier definition to look like the following
entity testWithVector is
port(
in1 : in std_logic_vector(63 downto 0);
in2 : in std_logic_vector(63 downto 0);
out1: out std_logic);
end entity;
*Notice that the expected input is a 64 bit wide signal path
*Assume that you have a Verilog reg as follows
reg [63:0] myReg;
reg [63:0] myOtherReg;
*Modlesim will let you directly map myReg to in1 or in2 (see below), however ISE will generally fail to compile this code, with an error about the expected size being incorrect
test t1(
.in1(myReg),
.in2(myOtherReg),
.out(myOutput)
);
*The easiest way around this is to map myReg to a wire, and use that in the instantiation of your VHDL module
wire [63:0] wire_myReg;
wire [63:0] wire_myOtherReg;
assign wire_myReg = myReg;
assign wire_myOtherReg = myOtherReg;

test t1(
.in1(wire_myReg),
.in2(wire_myOtherReg),
.out(myOutput)
);

== Include Option 1 ==
Use the USER_VHDL_FILES variable in the project makefile:

USER_VHDL_FILES += file1.vhd file2.vhd

The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled.

== Include Option 1.1 ==
Use the USER_VHDL_FILES variable in the project's top level Makefile.include:
USER_VHDL_FILES += ../vhdl/file.vhd
*Still use the ../ because this path will get included in the lower level directories, and the makefile there will still expect a relative path.

== Include Option 2 ==
Create site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile:

CNY_PDK_USER_DIRECTORY
CNY_PDK_SITE_DIRECTORY

This is a good place to set which simulator you use, set up signal tracing, etc.

== Other information ==
There are also several variables in the makefile that allow you to create dependencies for your own make flow. For example, the variable USER_SIM_DEPENDENCIES is listed as a dependency for the simulation, so if you want to run your own compile step before running the simulation, you can set that variable and the dependency will cause it to run that step at the right time. Others are USER_COMPILE_DEPENDENCIES and USER_PHYS_DEPENDENCIES, which is a dependency of the synthesis target.

Frequently Asked Questions

2013-02-04T21:35:35Z

Cnel711: /* How to run Modelsim GUI while simulating? */

== General FAQ ==

=== How to add new verilog files or directories to a PDK project? ===

By default, the PDK looks like the project/verilog directory and compiles all .v files found there. To add other Verilog directories, use this makefile variable:
<br /><nowiki>USER_VERILOG_DIRS += ../../verilog</nowiki>

=== How to run Modelsim GUI while simulating? ===
You may run the simulation in interactive mode by adding the following line to the makefile in the sim directory:

<code>USER_SIM_OPTIONS = -gui</code>

Another option is to edit the test bench (sim/tb_user.v shown below) to dump the waveforms to a file, then run the hardware simulator via command line, and finally open up the waveform file (vsim -v ./sim/vsim.wlf). This has the benefit of dumping all the signals (if your wave.do file was missing something, you'd have to rerun the simulation).

<nowiki>`timescale 1 ns / 1 ps

module tb_user();

initial begin
// Insert user code here, such as signal dumping
// set CNY_PDK_TB_USER_VLOG variable in sim/makefile
`include "PDK_SIM_CONFIG.vh"
`ifdef AE0_PRESENT
$wlfdumpvars(5,testbench.cae_fpga0.ae_top.core.cae_pers);
`endif
`ifdef AE1_PRESENT
$wlfdumpvars(5,testbench.cae_fpga1.ae_top.core.cae_pers);
`endif
`ifdef AE2_PRESENT
$wlfdumpvars(5,testbench.cae_fpga2.ae_top.core.cae_pers);
`endif
`ifdef AE3_PRESENT
$wlfdumpvars(5,testbench.cae_fpga3.ae_top.core.cae_pers);
`endif
end

endmodule
</nowiki>

== Emulator Related ==

=== How to read AEG registers in the emulator? ===
You can use the following function:
<code>
uint64 AegRead(int aeId, int aegIdx);
</code>

=== How to read/write the memory in the emulator? ===
You can use the functions AeMemLoad and AeMemStore to read and write from/to the memory as follows:

<code>
bool AeMemLoad (int aeId, int mcId, unint64 addr, int size, bool bSigned, uint64 &data); <br />
bool AeMemStore (int aeId, int mcId, unint64 addr, int size, bool bSigned, uint64 &data);
</code>

Using the Timing Analyzer

2012-12-05T14:58:25Z

Cnel711: /* Q. I know what module is causing timing issues... how can I just get timing data on 1 module instead of building the entire bitfile? */

Xilinx's Timing Analyzer can be used to find fixed timing errors with your design. If you design "works perfectly in simulation, but not in hardware", and when you build a bitfile and the timing constraints are not met, you have a timing error that needs fixed.

Good designs won't have timing errors, and there are tricks to writing good HDL code that results in good timing.

== Q. How do I know if my bitfile doesn't meet timing? ==

Check the Place and Route (phys/cae_fpga_routed.par) report in the phys folder or view the last few lines of the console output when building a bitfile. The timing results look something like this if you're failing to meet the timing constraints:

<nowiki>
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_ae_top_io_pll_clkout1 = PERIOD TIMEGRP | SETUP | -2.893ns| 9.560ns| 743| 498468
"ae_top_io_pll_clkout1" TS_CLK HIGH | HOLD | 0.000ns| | 0| 0
50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_ae_top_io_pll_clkout0 = PERIOD TIMEGRP | SETUP | 0.023ns| 3.310ns| 0| 0
"ae_top_io_pll_clkout0" TS_CLK / 2 | HOLD | 0.000ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------

...

1 constraint not met.
</nowiki>

If you're failing one of the Convey timing constraints, you need to rework your design. Sometimes you need to run the timing analyzer to find timing issues.

== Q. How do I know what's Causing the Timing Issue ==

If you're unsure of where the timing issue is, it makes sense to spend 10 minutes using the timing analyzer to find the longest critical paths in your design. Open the timing analyzer:

$ timingan &

Open your project: File -> Open Design. Select the final routed design and constraint files from the phys directory (.ncd, .pcf, .ngd, .ucf) from the most recent bitfile you created (yes... you have to build the bitfile first).

Run the analysis. Timing -> Run Analysis, Timing -> Report -> Net Delays, or (my favorite) Timing -> Query.

The report should list the critical path and it's setup/routing time. If it's near 6.67 ns, you just barely missed timing; perhaps registering the output of one of your modules is all you need. Another way to meet timing is to break up the steps into pipeline stages (i.e. if some logic block takes 20 ns, breaking it up into a few pipeline stages should help). If a route has high fanout, you can register the signal to reduce the fanout into a tree.

== Q. I know what module is causing timing issues... how can I just get timing data on 1 module instead of building the entire bitfile? ==

Start a new project in ISE with your module. The Timing Analyzer is available in the Tools file menu. You should add a .ucf file containing the period constraint of 150 MHz:

NET "clk" TNM_NET = "TN_CLK";
TIMESPEC "TS_CLK" = PERIOD "TN_CLK" 6.667 ns HIGH 50 %;

In this example, clk is the name of the net used as your clock signal.

== Other Advice ==
=== Reset, Set, Enable for Flip Flops ===
A world about flip-flops... the distributed flip-flops contain their own Reset, Set, and Enable signals, but have priority in that order (Reset > Set > Enable). If assigning data to flip-flops, try using this priority in your statements in order to use less logic. If your logic is not in this order, you may end up using extra LUTs.

<nowiki>
always @ (posedge clk) begin
if (reset)
d <= 0;
else if (set)
d <= 1;
else if (enable)
d <= YOUR COMBO LOGIC;
end
</nowiki>

=== Register Rebalancing ===
In synchronous designs, Xilinx XST can move logic forward or backward a register stage in order to balance the amount of work done in each register stage (thus improving timing). The side affects include radical changes to the structure of the design and an increase the synthesis run time. Modules with the Keep Heirarchy constraint will not rebalance registers.

To enable register rebalancing, you need to edit the template.xst file (/opt/convey/pdk/latest/phys/template.xst). If you don't have access, you can edit your project's copy of the template: phys/cae_fpga.xst by changing register_rebalancing to YES. Warning: After running '''make clean''' and '''make''', the original template will replace any user edits to the cae_fpga.xst file.

Using the Timing Analyzer

2012-12-04T19:11:25Z

Cnel711:

Xilinx's Timing Analyzer can be used to find fixed timing errors with your design. If you design "works perfectly in simulation, but not in hardware", and when you build a bitfile and the timing constraints are not met, you have a timing error that needs fixed.

Good designs won't have timing errors, and there are tricks to writing good HDL code that results in good timing.

== Q. How do I know if my bitfile doesn't meet timing? ==

Check the Place and Route (phys/cae_fpga_routed.par) report in the phys folder or view the last few lines of the console output when building a bitfile. The timing results look something like this if you're failing to meet the timing constraints:

<nowiki>
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_ae_top_io_pll_clkout1 = PERIOD TIMEGRP | SETUP | -2.893ns| 9.560ns| 743| 498468
"ae_top_io_pll_clkout1" TS_CLK HIGH | HOLD | 0.000ns| | 0| 0
50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_ae_top_io_pll_clkout0 = PERIOD TIMEGRP | SETUP | 0.023ns| 3.310ns| 0| 0
"ae_top_io_pll_clkout0" TS_CLK / 2 | HOLD | 0.000ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------

...

1 constraint not met.
</nowiki>

If you're failing one of the Convey timing constraints, you need to rework your design. Sometimes you need to run the timing analyzer to find timing issues.

== Q. How do I know what's Causing the Timing Issue ==

If you're unsure of where the timing issue is, it makes sense to spend 10 minutes using the timing analyzer to find the longest critical paths in your design. Open the timing analyzer:

$ timingan &

Open your project: File -> Open Design. Select the final routed design and constraint files from the phys directory (.ncd, .pcf, .ngd, .ucf) from the most recent bitfile you created (yes... you have to build the bitfile first).

Run the analysis. Timing -> Run Analysis, Timing -> Report -> Net Delays, or (my favorite) Timing -> Query.

The report should list the critical path and it's setup/routing time. If it's near 6.67 ns, you just barely missed timing; perhaps registering the output of one of your modules is all you need. Another way to meet timing is to break up the steps into pipeline stages (i.e. if some logic block takes 20 ns, breaking it up into a few pipeline stages should help). If a route has high fanout, you can register the signal to reduce the fanout into a tree.

== Q. I know what module is causing timing issues... how can I just get timing data on 1 module instead of building the entire bitfile? ==

Start a new project in ISE with your module. The Timing Analyzer is available in the Tools file menu, or you can just synthesize your module; the console gives a rough idea about the module's timing and max frequency (should be 150 MHz or more).

== Other Advice ==
=== Reset, Set, Enable for Flip Flops ===
A world about flip-flops... the distributed flip-flops contain their own Reset, Set, and Enable signals, but have priority in that order (Reset > Set > Enable). If assigning data to flip-flops, try using this priority in your statements in order to use less logic. If your logic is not in this order, you may end up using extra LUTs.

<nowiki>
always @ (posedge clk) begin
if (reset)
d <= 0;
else if (set)
d <= 1;
else if (enable)
d <= YOUR COMBO LOGIC;
end
</nowiki>

=== Register Rebalancing ===
In synchronous designs, Xilinx XST can move logic forward or backward a register stage in order to balance the amount of work done in each register stage (thus improving timing). The side affects include radical changes to the structure of the design and an increase the synthesis run time. Modules with the Keep Heirarchy constraint will not rebalance registers.

To enable register rebalancing, you need to edit the template.xst file (/opt/convey/pdk/latest/phys/template.xst). If you don't have access, you can edit your project's copy of the template: phys/cae_fpga.xst by changing register_rebalancing to YES. Warning: After running '''make clean''' and '''make''', the original template will replace any user edits to the cae_fpga.xst file.

Using the Timing Analyzer

2012-11-29T20:04:26Z

Cnel711: /* Other Advice */

Xilinx's Timing Analyzer can be used to find fixed timing errors with your design. If you design "works perfectly in simulation, but not in hardware", and when you build a bitfile and the timing constraints are not met, you have a timing error that needs fixed.

Good designs won't have timing errors, and there are tricks to writing good HDL code that results in good timing.

== Q. How do I know if my bitfile doesn't meet timing? ==

Check the Place and Route (phys/cae_fpga_routed.par) report in the phys folder or view the last few lines of the console output when building a bitfile. The timing results look something like this if you're failing to meet the timing constraints:

<nowiki>
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_ae_top_io_pll_clkout1 = PERIOD TIMEGRP | SETUP | -2.893ns| 9.560ns| 743| 498468
"ae_top_io_pll_clkout1" TS_CLK HIGH | HOLD | 0.000ns| | 0| 0
50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_ae_top_io_pll_clkout0 = PERIOD TIMEGRP | SETUP | 0.023ns| 3.310ns| 0| 0
"ae_top_io_pll_clkout0" TS_CLK / 2 | HOLD | 0.000ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------

...

1 constraint not met.
</nowiki>

If you're failing one of the Convey timing constraints, you need to rework your design. Sometimes you need to run the timing analyzer to find timing issues.

== Q. How do I know what's Causing the Timing Issue ==

If you're unsure of where the timing issue is, it makes sense to spend 10 minutes using the timing analyzer to find the longest critical paths in your design. Open the timing analyzer:

$ timingan &

Open your project: File -> Open Design. Select the final routed design and constraint files from the phys directory (.ncd, .pcf, .ngd, .ucf) from the most recent bitfile you created (yes... you have to build the bitfile first).

Run the analysis. Timing -> Run Analysis, Timing -> Report -> Net Delays, or (my favorite) Timing -> Query.

The report should list the critical path and it's setup/routing time. If it's near 6.67 ns, you just barely missed timing; perhaps registering the output of one of your modules is all you need. Another way to meet timing is to break up the steps into pipeline stages (i.e. if some logic block takes 20 ns, breaking it up into a few pipeline stages should help). If a route has high fanout, you can register the signal to reduce the fanout into a tree.

== Q. I know what module is causing timing issues... how can I just get timing data on 1 module instead of building the entire bitfile? ==

Start a new project in ISE with your module. The Timing Analyzer is available in the Tools file menu, or you can just synthesize your module; the console gives a rough idea about the module's timing and max frequency (should be 150 MHz or more).

== Other Advice ==
A world about flip-flops... the distributed flip-flops contain their own Reset, Set, and Enable signals, but have priority in that order (Reset > Set > Enable). If assigning data to flip-flops, try using this priority in your statements in order to use less logic. If your logic is not in this order, you may end up using extra LUTs.

<nowiki>
always @ (posedge clk) begin
if (reset)
d <= 0;
else if (set)
d <= 1;
else if (enable)
d <= YOUR COMBO LOGIC;
end
</nowiki>

Using the Timing Analyzer

2012-11-29T20:03:03Z

Cnel711: /* Q. I know what module is causing timing issues... how can I just get timing data on 1 module instead of building the entire bitfile? */

Xilinx's Timing Analyzer can be used to find fixed timing errors with your design. If you design "works perfectly in simulation, but not in hardware", and when you build a bitfile and the timing constraints are not met, you have a timing error that needs fixed.

Good designs won't have timing errors, and there are tricks to writing good HDL code that results in good timing.

== Q. How do I know if my bitfile doesn't meet timing? ==

Check the Place and Route (phys/cae_fpga_routed.par) report in the phys folder or view the last few lines of the console output when building a bitfile. The timing results look something like this if you're failing to meet the timing constraints:

<nowiki>
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_ae_top_io_pll_clkout1 = PERIOD TIMEGRP | SETUP | -2.893ns| 9.560ns| 743| 498468
"ae_top_io_pll_clkout1" TS_CLK HIGH | HOLD | 0.000ns| | 0| 0
50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_ae_top_io_pll_clkout0 = PERIOD TIMEGRP | SETUP | 0.023ns| 3.310ns| 0| 0
"ae_top_io_pll_clkout0" TS_CLK / 2 | HOLD | 0.000ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------

...

1 constraint not met.
</nowiki>

If you're failing one of the Convey timing constraints, you need to rework your design. Sometimes you need to run the timing analyzer to find timing issues.

== Q. How do I know what's Causing the Timing Issue ==

If you're unsure of where the timing issue is, it makes sense to spend 10 minutes using the timing analyzer to find the longest critical paths in your design. Open the timing analyzer:

$ timingan &

Open your project: File -> Open Design. Select the final routed design and constraint files from the phys directory (.ncd, .pcf, .ngd, .ucf) from the most recent bitfile you created (yes... you have to build the bitfile first).

Run the analysis. Timing -> Run Analysis, Timing -> Report -> Net Delays, or (my favorite) Timing -> Query.

The report should list the critical path and it's setup/routing time. If it's near 6.67 ns, you just barely missed timing; perhaps registering the output of one of your modules is all you need. Another way to meet timing is to break up the steps into pipeline stages (i.e. if some logic block takes 20 ns, breaking it up into a few pipeline stages should help). If a route has high fanout, you can register the signal to reduce the fanout into a tree.

== Q. I know what module is causing timing issues... how can I just get timing data on 1 module instead of building the entire bitfile? ==

Start a new project in ISE with your module. The Timing Analyzer is available in the Tools file menu, or you can just synthesize your module; the console gives a rough idea about the module's timing and max frequency (should be 150 MHz or more).

== Other Advice ==
A world about flip-flops... the distributed flip-flops contain their own Reset, Set, and Enable signals, but have that priority. If assigning data to flip-flops, try using this priority in your statements in order to use less logic. If your logic is not in this order, you may end up using extra LUTs.

<nowiki>
always @ (posedge clk) begin
if (reset)
d <= 0;
else if (set)
d <= 1;
else if (enable)
d <= YOUR COMBO LOGIC;
end
</nowiki>

Running the Vector Adder Example Application

2012-11-29T20:01:21Z

Cnel711: /* Interactive Mode for ModelSim Simulation */

Section 10.5 of the [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] explains how to run the sample software application. It has been reproduced below in brief.

== Compiling the Project ==
The rev version installed on the Convey machine is from 2012-03-19; to copy the sample app's source code run:
cd ~
mkdir pdk_sample
cp -r /opt/convey/pdk/latest/hc-1/examples/* pdk_sample

To make the sample project, first make sure you have [[Convey environment setup|setup your environment variables]], then run:

cd ~/pdk_sample/cae_pers_vadd/SampleAppVadd/
make

This compiles both an emulator (CaeSimPers) and a C program that makes a coprocessor call to use the vector adder (UserApp.exe).

== Run the Project ==
There are three ways to run your project:
# A software simulation of the FPGA design
# A hardware simulation (ModelSim) of the FPGA design
# The actual implementation (C code, Verilog code). The bitfile was previously compiled, nicknamed, and added to a known file location (/opt/convey/personalties/...).

There are some scripts that can be used to run the various projects.

The '''runcp''' (i.e. run coprocessor) script located in the SampleAppVadd can be used to run the application in HW which sets the appropriate environment variables and runs the UserApp.exe:

./runcp

The '''run''' script located in the SampleAppVadd can be used to run the application using the software simulation of the FPGA design.

./run

Using the "-vsim" option, either script can be used to run the application using the hardware simulation (ModelSim). The "-vsim" option sets the environment variable CNY_CAE_EMULATOR to ./run_simulation:

./runcp -vsim
or
./run -vsim

To summarize the important environment variables:

{| border="1" cellpadding="5" cellspacing="0"
|-
|'''Environment Variables''' || '''Software''' || '''ModelSim''' || '''Hardware'''
|-
|CNY_SIM_THREAD || libcpSimLib2.so || libcpSimLib2.so || ''unset''
|-
|CNY_CAE_EMULATOR || <location for CaeSimPers> || ./run_simulation || ''unset''
|}

=== Interactive Mode for ModelSim Simulation ===
Source: http://www.conveysupport.com/help/?p=215

You can save the waveforms every time you run the hardware simulator to make debugging easier.

Add the $wlfdumpvars line to the sim/tb_user.v file:
// To trace everything (slow)
$wlfdumpvars(0, testbench);
// To trace cae_pers module and 5 levels below
`ifdef AE0_PRESENT
$wlfdumpvars(5,testbench.cae_fpga0.ae_top.core.cae_pers);

Then include that file in the sim/Makefile by adding this line this line:
CNY_PDK_TB_USER_VLOG += ./tb_user.v

This will create a vsim.wlf file in the sim directory. You can view the waveform using any of the following terminal commands:
vsim ../sim/vsim.wlf
vsim -view ../sim/vsim.wlf

Alternatively, you may instead run the simulation in interactive mode by adding the following line to the makefile:
USER_SIM_OPTIONS = -gui
Then run the app (./run -vsim) to start the simulation. When the Modelsim GUI opens and the design is loaded, type “run -all” at the Modelsim command line.

Tutorial: Creating a Custom Bitfile

2012-11-29T19:59:59Z

Cnel711: /* Choose a New Signature */

This page covers the creation and installation of a custom personality/bitfile (a modification of the vector adder sample project).

== Building a Bitfile ==
Copy the newest version of the [[Running the Vector Adder Example Application#Compiling the Project|example project]] and set your [[Convey environment setup|environment variables]] if you have not done so already. You can make a small modification to the verilog code if you wish, such as making it a vector subtractor instead of a vector adder.

Next, compile your bitfile:

cd ~/pdk_sample/cae_vadd/phys
make

The bitfile will take a long time to create (while the Reference Manual states 2 to 4 hours, it may take much longer). Be patient.

Next, package your bitfile using the command:

make release

=== FPGA Usage Statistics ===

The device usage statistics are displayed on the terminal while building the bitfile. The log is saved to disk at:

{project directory}/phys/cae_fpga.map
OR
{project directory}/phys/cae_fpga.par

Search the end of the log file for "Design Summay" for a percentage break down in LUT, Flip flop, and BRAM usage.

== Choose a New Signature ==
Custom personalities should not use the default PDK signature (4.1.1.1.0). Choose a new signature between 65000 and 65535. In this example, we will use 65123.1.1.1.0.

You will need to create a new directory and copy the pertinent files to this directory:

cd /opt/convey/personalities
mkdir 65123.1.1.1.0
cd 65123.1.1.1.0

cp /home/PROJECT_RELEASE/DATE/cae_fpga.tgz ./ae_fpga.tgz

This is the only required file, but you may copy PersDesc.dat from the default PDK folder to your new folder and uncomment additional custom instructions you have used.

cp /opt/convey/personalities/4.1.1.1.0/PersDesc.dat ./

Instead of adding a new directory to Convey's personality folder as done above, you may set the CNY_PERSONALITY_PATH environment variable to any directory, i.e.

export CNY_PERSONALITY_PATH=/home/PROJECT_PATH/
or
setenv CNY_PERSONALITY_PATH /home/PROJECT_PATH/

The default when the CNY_PERSONALITY_PATH is not set is to use the /opt/convey/personalities folder.

You will also need to update the ''customdb'' file in /opt/convey/personalities (or create your own customdb file in your user defined personalities folder). This file is used by the cny_get_signature function and converts strings to a signature number. Our customdb file contains the following text:

65123.1.1.1.0,subtractor

Finally, there are certain places in the code where you should ensure that the signature has been updated.

* In the simulator (/sim/CaeIsaVadd.cpp), update: '''#define PERS_SIGN_CAE 0xfe63001000101000LL''', where 0xfe63 is the hex value for your signature (65123).
* In the C code, (SampleAppVadd/UserApp.c) update: '''cny_get_signature("subtractor", &sig, &sig2, &stat);''', where "subtractor" is the pseudo name of your CAE given in the customdb file.
* In the assembly code, (SampleAppVadd/cpVadd.s) update the signature directive: '''.signature pdk=65123'''

When you change the personalities directory, flush the MP cache. This will erase the cache, which is necessary if you've updated your custom bitfile:

/opt/convey/sbin/mpcache -f

You can also add a signature, and preload a given bitfile by using the commands:

/opt/convey/sbin/mpcache -add -S<personality>
/opt/convey/sbin/mpcache -load -S<personality>

Additional details are available in Appendix D of the [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]].

== See Also ==
* [[Using a Custom Bitfile in C Code]]

== References ==
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] - Sections 9.4.6, 9.4.7, 10, Appendix D

Tutorial: Creating a Custom Bitfile

2012-11-29T19:58:17Z

Cnel711: /* FPGA Usage Statistics */

This page covers the creation and installation of a custom personality/bitfile (a modification of the vector adder sample project).

== Building a Bitfile ==
Copy the newest version of the [[Running the Vector Adder Example Application#Compiling the Project|example project]] and set your [[Convey environment setup|environment variables]] if you have not done so already. You can make a small modification to the verilog code if you wish, such as making it a vector subtractor instead of a vector adder.

Next, compile your bitfile:

cd ~/pdk_sample/cae_vadd/phys
make

The bitfile will take a long time to create (while the Reference Manual states 2 to 4 hours, it may take much longer). Be patient.

Next, package your bitfile using the command:

make release

=== FPGA Usage Statistics ===

The device usage statistics are displayed on the terminal while building the bitfile. The log is saved to disk at:

{project directory}/phys/cae_fpga.map
OR
{project directory}/phys/cae_fpga.par

Search the end of the log file for "Design Summay" for a percentage break down in LUT, Flip flop, and BRAM usage.

== Choose a New Signature ==
Custom personalities should not use the default PDK signature (4.1.1.1.0). Choose a new signature between 65000 and 65535. In this example, we will use 65123.1.1.1.0.

You will need to create a new directory and copy the pertinent files to this directory:

cd /opt/convey/personalities
mkdir 65123.1.1.1.0
cd 65123.1.1.1.0

cp /home/PROJECT_RELEASE/DATE/cae_fpga.tgz ./ae_fpga.tgz

This is the only required file, but you may copy PersDesc.dat from the default PDK folder to your new folder and uncomment additional custom instructions you have used.

cp /opt/convey/personalities/4.1.1.1.0/PersDesc.dat ./

Instead of adding a new directory to Convey's personality folder as done above, you may set the CNY_PERSONALITY_PATH environment variable to any directory, i.e.

export CNY_PERSONALITY_PATH=/home/PROJECT_PATH/
or
setenv CNY_PERSONALITY_PATH /home/PROJECT_PATH/

The default when the CNY_PERSONALITY_PATH is not set is to use the /opt/convey/personalities folder.

You will also need to update the ''customdb'' file in /opt/convey/personalities (or create your own customdb file in your user defined personalities folder). This file is used by the cny_get_signature function and converts strings to a signature number. Our customdb file contains the following text:

65123.1.1.1.0,subtractor

Finally, there are certain places in the code where you should ensure that the signature has been updated.

* In the simulator (/sim/CaeIsaVadd.cpp), update: '''#define PERS_SIGN_CAE 0xfe63001000101000LL''', where 0xfe63 is the hex value for your signature (65123).
* In the C code, (SampleAppVadd/UserApp.c) update: '''cny_get_signature("subtractor", &sig, &sig2, &stat);''', where "subtractor" is the pseudo name of your CAE given in the customdb file.
* In the assembly code, (SampleAppVadd/cpVadd.s) update the signature directive: '''.signature pdk=65123'''

When you change the personalities directory, flush the MP cache. This will unload the current bitfile:

/opt/convey/sbin/mpcache -f

You can also add a signature, and preload a given bitfile by using the commands:

/opt/convey/sbin/mpcache -add -S<personality>
/opt/convey/sbin/mpcache -load -S<personality>

Additional details are available in Appendix D of the [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]].

== See Also ==
* [[Using a Custom Bitfile in C Code]]

== References ==
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] - Sections 9.4.6, 9.4.7, 10, Appendix D

Main Page

2012-11-08T18:15:18Z

Cnel711: /* Convey */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Running the Vector Adder Example Application]]
* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]
* [[Using the Write-Complete Interface]]
* [[Using the Timing Analyzer]]

* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://www.asic-world.com www.asic-world.com] - Great Tutorials for those Learning HDLs
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://www.c7t-hdl.com/Docs/C7T_AN05_Customized_WaveView_ModelSim_ISE.pdf Modelsim and ISE]
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]

Main Page

2012-11-08T00:32:23Z

Cnel711: /* Helpful Guides */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Running the Vector Adder Example Application]]
* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]
* [[Using the Write-Complete Interface]]
* [[Using the Timing Analyzer]]

* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://www.asic-world.com www.asic-world.com] - Great Tutorials for those Learning HDLs
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://www.c7t-hdl.com/Docs/C7T_AN05_Customized_WaveView_ModelSim_ISE.pdf Modelsim and ISE]
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]

Using the Timing Analyzer

2012-11-06T16:01:20Z

Cnel711:

Xilinx's Timing Analyzer can be used to find fixed timing errors with your design. If you design "works perfectly in simulation, but not in hardware", and when you build a bitfile and the timing constraints are not met, you have a timing error that needs fixed.

Good designs won't have timing errors, and there are tricks to writing good HDL code that results in good timing.

== Q. How do I know if my bitfile doesn't meet timing? ==

Check the Place and Route (phys/cae_fpga_routed.par) report in the phys folder or view the last few lines of the console output when building a bitfile. The timing results look something like this if you're failing to meet the timing constraints:

<nowiki>
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_ae_top_io_pll_clkout1 = PERIOD TIMEGRP | SETUP | -2.893ns| 9.560ns| 743| 498468
"ae_top_io_pll_clkout1" TS_CLK HIGH | HOLD | 0.000ns| | 0| 0
50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_ae_top_io_pll_clkout0 = PERIOD TIMEGRP | SETUP | 0.023ns| 3.310ns| 0| 0
"ae_top_io_pll_clkout0" TS_CLK / 2 | HOLD | 0.000ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------

...

1 constraint not met.
</nowiki>

If you're failing one of the Convey timing constraints, you need to rework your design. Sometimes you need to run the timing analyzer to find timing issues.

== Q. How do I know what's Causing the Timing Issue ==

If you're unsure of where the timing issue is, it makes sense to spend 10 minutes using the timing analyzer to find the longest critical paths in your design. Open the timing analyzer:

$ timingan &

Open your project: File -> Open Design. Select the final routed design and constraint files from the phys directory (.ncd, .pcf, .ngd, .ucf) from the most recent bitfile you created (yes... you have to build the bitfile first).

Run the analysis. Timing -> Run Analysis, Timing -> Report -> Net Delays, or (my favorite) Timing -> Query.

The report should list the critical path and it's setup/routing time. If it's near 6.67 ns, you just barely missed timing; perhaps registering the output of one of your modules is all you need. Another way to meet timing is to break up the steps into pipeline stages (i.e. if some logic block takes 20 ns, breaking it up into a few pipeline stages should help). If a route has high fanout, you can register the signal to reduce the fanout into a tree.

== Q. I know what module is causing timing issues... how can I just get timing data on 1 module instead of building the entire bitfile? ==

Start a new project in ISE with your module. The Timing Analyzer is available in the Tools file menu, or you can just synthesize your module to get a rough idea about it's timing.

== Other Advice ==
A world about flip-flops... the distributed flip-flops contain their own Reset, Set, and Enable signals, but have that priority. If assigning data to flip-flops, try using this priority in your statements in order to use less logic. If your logic is not in this order, you may end up using extra LUTs.

<nowiki>
always @ (posedge clk) begin
if (reset)
d <= 0;
else if (set)
d <= 1;
else if (enable)
d <= YOUR COMBO LOGIC;
end
</nowiki>

Using ISE's Core Generator to build FIFOs and other IP cores

2012-11-06T02:08:54Z

Cnel711: /* Why Use Dedicated Logic */

== Why Use Dedicated Logic ==
If you don't use it, you lose it! Don't let the dedicated logic (BRAMs, DSP slices) go unused... you'll hurt their feelings.

Dedicated logic improves compile times and reduces the amount of Slice Logic used. It's also FAST, and can help reduce the chance of timing errors. For example, the DSP slices can operate at 550 MHz.

== How-to ==
# Open Xilinx's ISE from the terminal (make sure your [[Convey environment setup | environmental variables]] are set):
ise &
# Create or open a project. The devices on the HC-1 and HC-2 are Virtex 5 FPGAs (xc5vlx330, -2, ff1760).
# Open the Core Generator (Tools -> Core Generator...)
# Create a new Core Generator project.
## Part
### Family: Virtex5
### Device: xc5vlx330
### Package: ff1760
### Speed: -2
## Generation
### Simulation Model: Structural
# Generate you IP Cores!
# Copy the .ngc, .v, and .xco to the coregen folder in your PDK project

== Common IP Cores ==
Most IP cores can be implemented using either BRAM (Block RAM), DSP cores, or Slice logic. To give you an idea about the number of components available, there are:
* 288 36-Kilobit BRAMs available
** BRAMs are dual port, allowing multiple small FIFOs per BRAM
* 28x15 DSP slices
* 51,840 Slices (each slice contains 4 LUTS & 4 Flip-flops)

Here are some common components you could use:
* Memories & Storage Elements -> (use Block RAM)
** FIFOs (any port width)
** Dual port RAM (port widths: 2, 4, 8... up to 128 bits)
* Math Functions -> (use DSP slices)
** Adder/Subtracts (up to 48 bit)
** Multipliers (up to 64 bit, 128 bit output)
** Dividers (up to 32 bit)

Using ISE's Core Generator to build FIFOs and other IP cores

2012-11-06T02:01:58Z

Cnel711:

== Why Use Dedicated Logic ==
If you don't use it, you lose it! Don't let the dedicated logic (BRAMs, DSP cores) go unused... you'll hurt their feelings.

Dedicated logic improves compile times and reduces the amount of Slice Logic used. It's also FAST, and can help reduce the chance of timing errors.

== How-to ==
# Open Xilinx's ISE from the terminal (make sure your [[Convey environment setup | environmental variables]] are set):
ise &
# Create or open a project. The devices on the HC-1 and HC-2 are Virtex 5 FPGAs (xc5vlx330, -2, ff1760).
# Open the Core Generator (Tools -> Core Generator...)
# Create a new Core Generator project.
## Part
### Family: Virtex5
### Device: xc5vlx330
### Package: ff1760
### Speed: -2
## Generation
### Simulation Model: Structural
# Generate you IP Cores!
# Copy the .ngc, .v, and .xco to the coregen folder in your PDK project

== Common IP Cores ==
Most IP cores can be implemented using either BRAM (Block RAM), DSP cores, or Slice logic. To give you an idea about the number of components available, there are:
* 288 36-Kilobit BRAMs available
** BRAMs are dual port, allowing multiple small FIFOs per BRAM
* 28x15 DSP slices
* 51,840 Slices (each slice contains 4 LUTS & 4 Flip-flops)

Here are some common components you could use:
* Memories & Storage Elements -> (use Block RAM)
** FIFOs (any port width)
** Dual port RAM (port widths: 2, 4, 8... up to 128 bits)
* Math Functions -> (use DSP slices)
** Adder/Subtracts (up to 48 bit)
** Multipliers (up to 64 bit, 128 bit output)
** Dividers (up to 32 bit)

Main Page

2012-11-04T04:20:33Z

Cnel711: /* Links */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Running the Vector Adder Example Application]]
* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]
* [[Using the Write-Complete Interface]]
* [[Using the Timing Analyzer]]

* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://www.asic-world.com www.asic-world.com] - Great Tutorials for those Learning HDLs
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]

Main Page

2012-11-04T04:20:14Z

Cnel711: /* Links */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Running the Vector Adder Example Application]]
* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]
* [[Using the Write-Complete Interface]]
* [[Using the Timing Analyzer]]

* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://www.asic-world.com] Great Tutorials for those Learning HDLs
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]

Using the Timing Analyzer

2012-11-02T18:46:07Z

Cnel711:

Running the Vector Adder Example Application

2012-11-01T22:06:44Z

Cnel711: /* Interactive Mode for ModelSim Simulation */

Running the Vector Adder Example Application

2012-11-01T22:00:58Z

Cnel711: /* Interactive Mode for ModelSim Simulation */

Section 10.5 of the [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] explains how to run the sample software application. It has been reproduced below in brief.

== Compiling the Project ==
The rev version installed on the Convey machine is from 2012-03-19; to copy the sample app's source code run:
cd ~
mkdir pdk_sample
cp -r /opt/convey/pdk/latest/hc-1/examples/* pdk_sample

To make the sample project, first make sure you have [[Convey environment setup|setup your environment variables]], then run:

cd ~/pdk_sample/cae_pers_vadd/SampleAppVadd/
make

This compiles both an emulator (CaeSimPers) and a C program that makes a coprocessor call to use the vector adder (UserApp.exe).

== Run the Project ==
There are three ways to run your project:
# A software simulation of the FPGA design
# A hardware simulation (ModelSim) of the FPGA design
# The actual implementation (C code, Verilog code). The bitfile was previously compiled, nicknamed, and added to a known file location (/opt/convey/personalties/...).

There are some scripts that can be used to run the various projects.

The '''runcp''' (i.e. run coprocessor) script located in the SampleAppVadd can be used to run the application in HW which sets the appropriate environment variables and runs the UserApp.exe:

./runcp

The '''run''' script located in the SampleAppVadd can be used to run the application using the software simulation of the FPGA design.

./run

Using the "-vsim" option, either script can be used to run the application using the hardware simulation (ModelSim). The "-vsim" option sets the environment variable CNY_CAE_EMULATOR to ./run_simulation:

./runcp -vsim
or
./run -vsim

To summarize the important environment variables:

{| border="1" cellpadding="5" cellspacing="0"
|-
|'''Environment Variables''' || '''Software''' || '''ModelSim''' || '''Hardware'''
|-
|CNY_SIM_THREAD || libcpSimLib2.so || libcpSimLib2.so || ''unset''
|-
|CNY_CAE_EMULATOR || <location for CaeSimPers> || ./run_simulation || ''unset''
|}

=== Interactive Mode for ModelSim Simulation ===
Source: http://www.conveysupport.com/help/?p=215

You can save the waveforms every time you run the hardware simulator to make debugging easier.

Add the $wlfdumpvars line to the sim/tb_user.v file:
// To trace everything (slow)
$wlfdumpvars(0, testbench);
// To trace cae_pers module and 5 levels below
`ifdef AE0_PRESENT
$wlfdumpvars(5,testbench.cae_fpga0.ae_top.core.cae_pers);

Then include that file in the sim/Makefile by adding this line this line:
CNY_PDK_TB_USER_VLOG += ./tb_user.v

This will create a vsim.wlf file in the sim directory. You can view the waveform using any of the following terminal commands:
vsim ../sim/vsim.wlf
vsim -view ../sim/vsim.wlf
vsim -wlf (if in /sim directory)
vsim -wlf -do wave.do

Using the Timing Analyzer

2012-11-01T21:03:02Z

Cnel711: /* Q. How do I know what's Causing the Timing Issue */

Using the Timing Analyzer

2012-11-01T05:25:19Z

Cnel711: /* Q. How do I know what's Causing the Timing Issue */

Using the Timing Analyzer

2012-11-01T05:11:59Z

Cnel711:

Using the Timing Analyzer

2012-11-01T01:52:37Z

Cnel711: /* How do I know what's Causing the Timing Issue */

Using the Timing Analyzer

2012-11-01T01:52:22Z

Cnel711: New page: Xilinx's Timing Analyzer can be used to find fixed timing errors with your design. If you design "works perfectly in simulation, but not in hardware", and when you build a bitfile and the...

Main Page

2012-11-01T01:34:48Z

Cnel711: /* Convey HC-1 Tutorials */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Running the Vector Adder Example Application]]
* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]
* [[Using the Write-Complete Interface]]
* [[Using the Timing Analyzer]]

* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]

Analyze the Simpleton Basic App

2012-10-29T04:06:36Z

Cnel711:

Download the simpleton app:

<nowiki>
svn co http://svn.chaddington.com/simpleton</nowiki>

Follow the [[Running the Vector Adder Example Application | vector adder example]] for how to make and run the project.

Open and analyze the following files, learn the directory structure, etc:

* /cae_simpleton/src/run
* /cae_simpleton/src/runcp
* /cae_simpleton/src/Userapp.c
* /cae_simpleton/src/cp.s
* /cae_simpleton/sim/CaeIsa.cpp
* /cae_simpleton/verilog/personality.v
* /cae_simpleton/coregen/README
* /cae_simpleton/phys
* /cae_simpleton/makefile.include
* /personalities/customdb
* /personalities/65100.1.1.0/

Using the Write-Complete Interface

2012-10-29T04:05:04Z

Cnel711: New page: There's an optional (advanced) interface for indicating when a write completes (along with the ability to send 17 bits of write-complete control data with the write request in order to ID ...

There's an optional (advanced) interface for indicating when a write completes (along with the ability to send 17 bits of write-complete control data with the write request in order to ID the requests). Use of the interface means the write flush interface is not available.

To enable, edit the main project makefile to set the appropriate environment variable:
export MC_WR_CMP_IF = 1

The ports to the cae_pers module must be modified; the scripts that compile verilog for both the hardware simulator and for building a bitfile will define "MC_WR_CMP_IF" inside of "pdk_fpga_defines.vh".

<nowiki>
// Top of file (already included)
`include "pdk_fpga_defines.vh"

// ...

// Part of the cae_pers module port declaration
`ifdef MC_WR_CMP_IF
output [16:0] mc0_req_wrctl_e, mc0_req_wrctl_o,
output mc0_wr_rsp_stall_e, mc0_wr_rsp_stall_o,
input mc0_rsp_wrcmp_e, mc0_rsp_wrcmp_o,
input [16:0] mc0_rsp_wrctl_e, mc0_rsp_wrctl_o,
output [16:0] mc1_req_wrctl_e, mc1_req_wrctl_o,
output mc1_wr_rsp_stall_e, mc1_wr_rsp_stall_o,
input mc1_rsp_wrcmp_e, mc1_rsp_wrcmp_o,
input [16:0] mc1_rsp_wrctl_e, mc1_rsp_wrctl_o,
output [16:0] mc2_req_wrctl_e, mc2_req_wrctl_o,
output mc2_wr_rsp_stall_e, mc2_wr_rsp_stall_o,
input mc2_rsp_wrcmp_e, mc2_rsp_wrcmp_o,
input [16:0] mc2_rsp_wrctl_e, mc2_rsp_wrctl_o,
output [16:0] mc3_req_wrctl_e, mc3_req_wrctl_o,
output mc3_wr_rsp_stall_e, mc3_wr_rsp_stall_o,
input mc3_rsp_wrcmp_e, mc3_rsp_wrcmp_o,
input [16:0] mc3_rsp_wrctl_e, mc3_rsp_wrctl_o,
output [16:0] mc4_req_wrctl_e, mc4_req_wrctl_o,
output mc4_wr_rsp_stall_e, mc4_wr_rsp_stall_o,
input mc4_rsp_wrcmp_e, mc4_rsp_wrcmp_o,
input [16:0] mc4_rsp_wrctl_e, mc4_rsp_wrctl_o,
output [16:0] mc5_req_wrctl_e, mc5_req_wrctl_o,
output mc5_wr_rsp_stall_e, mc5_wr_rsp_stall_o,
input mc5_rsp_wrcmp_e, mc5_rsp_wrcmp_o,
input [16:0] mc5_rsp_wrctl_e, mc5_rsp_wrctl_o,
output [16:0] mc6_req_wrctl_e, mc6_req_wrctl_o,
output mc6_wr_rsp_stall_e, mc6_wr_rsp_stall_o,
input mc6_rsp_wrcmp_e, mc6_rsp_wrcmp_o,
input [16:0] mc6_rsp_wrctl_e, mc6_rsp_wrctl_o,
output [16:0] mc7_req_wrctl_e, mc7_req_wrctl_o,
output mc7_wr_rsp_stall_e, mc7_wr_rsp_stall_o,
input mc7_rsp_wrcmp_e, mc7_rsp_wrcmp_o,
input [16:0] mc7_rsp_wrctl_e, mc7_rsp_wrctl_o,
`else
output mc0_req_flush_e, mc0_req_flush_o,
input mc0_rsp_flush_cmplt_e, mc0_rsp_flush_cmplt_o,
output mc1_req_flush_e, mc1_req_flush_o,
input mc1_rsp_flush_cmplt_e, mc1_rsp_flush_cmplt_o,
output mc2_req_flush_e, mc2_req_flush_o,
input mc2_rsp_flush_cmplt_e, mc2_rsp_flush_cmplt_o,
output mc3_req_flush_e, mc3_req_flush_o,
input mc3_rsp_flush_cmplt_e, mc3_rsp_flush_cmplt_o,
output mc4_req_flush_e, mc4_req_flush_o,
input mc4_rsp_flush_cmplt_e, mc4_rsp_flush_cmplt_o,
output mc5_req_flush_e, mc5_req_flush_o,
input mc5_rsp_flush_cmplt_e, mc5_rsp_flush_cmplt_o,
output mc6_req_flush_e, mc6_req_flush_o,
input mc6_rsp_flush_cmplt_e, mc6_rsp_flush_cmplt_o,
output mc7_req_flush_e, mc7_req_flush_o,
input mc7_rsp_flush_cmplt_e, mc7_rsp_flush_cmplt_o,
`endif
</nowiki>

Main Page

2012-10-29T03:58:27Z

Cnel711: /* Articles */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Running the Vector Adder Example Application]]
* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]
* [[Using the Write-Complete Interface]]
* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]

Running Different Bitfiles on each AE

2012-10-29T03:57:29Z

Cnel711:

The PDK is setup to help you rapidly test and develop a single bitfile. Thus, projects requiring multiple bitfiles should have multiple PDK sub-projects.

== Running different bitfiles on each AE ==
Source: http://www.ccm.ece.vt.edu/twiki/bin/view/Main/Convey
Source: http://www.conveysupport.com/help/?p=178

The runtime environment supports multiple bitfiles making up a single personality (i.e. different ). There is a script called "mkaetgz" that is installed on the HC-1 system. To use it, you need to create a project for each bitfile. Then run the script to package them into one personality.

/opt/convey/sbin/mkaetgz -h
mkaetgz [-i <initFile>] [-f <file0,file1,...,fileN>] [-F] [-h]
[-o <tgz name>] [-t <tmpDir>] [-v]
-0 <aeImage0> [-1 <aeImage1> -2 <aeImage2> -3 <aeImage3>]

For example:
mkaetgz -i /opt/convey/pdk/2010_08_09/doc/cae_init.txt -0 cae_fpga0.bit -1 cae_fpga1.bit -2 cae_fpga2.bit -3 cae_fpga3.bit

Note: If mkaetgz does not exist, you can download a copy of the bash script here: [[Media:Mkaetgz.txt | mkaetgz]]

There's also a CNY_LOAD_IMAGE environment variable you can set with the first image you want loaded on the coprocessor (export CNY_LOAD_IMAGE=65200.1.1.1).

Running the Vector Adder Example Application

2012-10-22T04:51:23Z

Cnel711: /* Interactive Mode for ModelSim Simulation */

Section 10.5 of the [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] explains how to run the sample software application. It has been reproduced below in brief.

== Compiling the Project ==
The rev version installed on the Convey machine is from 2012-03-19; to copy the sample app's source code run:
cd ~
mkdir pdk_sample
cp -r /opt/convey/pdk/latest/hc-1/examples/* pdk_sample

To make the sample project, first make sure you have [[Convey environment setup|setup your environment variables]], then run:

cd ~/pdk_sample/cae_pers_vadd/SampleAppVadd/
make

This compiles both an emulator (CaeSimPers) and a C program that makes a coprocessor call to use the vector adder (UserApp.exe).

== Run the Project ==
There are three ways to run your project:
# A software simulation of the FPGA design
# A hardware simulation (ModelSim) of the FPGA design
# The actual implementation (C code, Verilog code). The bitfile was previously compiled, nicknamed, and added to a known file location (/opt/convey/personalties/...).

There are some scripts that can be used to run the various projects.

The '''runcp''' (i.e. run coprocessor) script located in the SampleAppVadd can be used to run the application in HW which sets the appropriate environment variables and runs the UserApp.exe:

./runcp

The '''run''' script located in the SampleAppVadd can be used to run the application using the software simulation of the FPGA design.

./run

Using the "-vsim" option, either script can be used to run the application using the hardware simulation (ModelSim). The "-vsim" option sets the environment variable CNY_CAE_EMULATOR to ./run_simulation:

./runcp -vsim
or
./run -vsim

To summarize the important environment variables:

{| border="1" cellpadding="5" cellspacing="0"
|-
|'''Environment Variables''' || '''Software''' || '''ModelSim''' || '''Hardware'''
|-
|CNY_SIM_THREAD || libcpSimLib2.so || libcpSimLib2.so || ''unset''
|-
|CNY_CAE_EMULATOR || <location for CaeSimPers> || ./run_simulation || ''unset''
|}

=== Interactive Mode for ModelSim Simulation ===
Source: http://www.conveysupport.com/help/?p=215

You can save the waveforms every time you run the hardware simulator to make debugging easier.

Add the $wlfdumpvars line to the sim/tb_user.v file:
// To trace everything
$wlfdumpvars(0, testbench);
// To trace cae_pers module and 5 levels below
$wlfdumpvars(5,testbench.cae_fpga0.ae_top.core.cae_pers);

Then include that file in the sim/Makefile by adding this line this line:
CNY_PDK_TB_USER_VLOG += ./tb_user.v

This will create a vsim.wlf file in the sim directory. You can view the waveform using the terminal command
vsim -view ../sim/vsim.wlf

Main Page

2012-10-22T00:31:38Z

Cnel711: /* Helpful Guides */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Running the Vector Adder Example Application]]
* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]
* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]

Running Different Bitfiles on each AE

2012-09-25T23:50:30Z

Cnel711:

File:Mkaetgz.txt

2012-09-25T23:48:17Z

Cnel711:

Running the Vector Adder Example Application

2012-09-25T23:39:12Z

Cnel711: /* Interactive Mode for ModelSim Simulation */

Section 10.5 of the [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] explains how to run the sample software application. It has been reproduced below in brief.

== Compiling the Project ==
The rev version installed on the Convey machine is from 2012-03-19; to copy the sample app's source code run:
cd ~
mkdir pdk_sample
cp -r /opt/convey/pdk/latest/hc-1/examples/* pdk_sample

To make the sample project, first make sure you have [[Convey environment setup|setup your environment variables]], then run:

cd ~/pdk_sample/cae_pers_vadd/SampleAppVadd/
make

This compiles both an emulator (CaeSimPers) and a C program that makes a coprocessor call to use the vector adder (UserApp.exe).

== Run the Project ==
There are three ways to run your project:
# A software simulation of the FPGA design
# A hardware simulation (ModelSim) of the FPGA design
# The actual implementation (C code, Verilog code). The bitfile was previously compiled, nicknamed, and added to a known file location (/opt/convey/personalties/...).

There are some scripts that can be used to run the various projects.

The '''runcp''' (i.e. run coprocessor) script located in the SampleAppVadd can be used to run the application in HW which sets the appropriate environment variables and runs the UserApp.exe:

./runcp

The '''run''' script located in the SampleAppVadd can be used to run the application using the software simulation of the FPGA design.

./run

Using the "-vsim" option, either script can be used to run the application using the hardware simulation (ModelSim). The "-vsim" option sets the environment variable CNY_CAE_EMULATOR to ./run_simulation:

./runcp -vsim
or
./run -vsim

To summarize the important environment variables:

{| border="1" cellpadding="5" cellspacing="0"
|-
|'''Environment Variables''' || '''Software''' || '''ModelSim''' || '''Hardware'''
|-
|CNY_SIM_THREAD || libcpSimLib2.so || libcpSimLib2.so || ''unset''
|-
|CNY_CAE_EMULATOR || <location for CaeSimPers> || ./run_simulation || ''unset''
|}

=== Interactive Mode for ModelSim Simulation ===
Source: http://www.conveysupport.com/help/?p=215

The sample project will default to command line mode when using the -vsim flag. Add the following line in the ./sim/Makefile to have it start in interactive mode:

USER_SIM_OPTIONS = -i

You can find the custom personality under testbench->cae_fpga->ae_top->core->cae_pers. Once you have a wave format that you want to automatically load, save it (File->Save Format).

Alternatively, add the $wlfdumpvars line to the sim/tb_user.v file:
// To trace everything
$wlfdumpvars(0, testbench);
// To trace cae_pers module and 5 levels below
$wlfdumpvars(5,testbench.cae_fpga0.ae_top.core.cae_pers);

Then include that file in the sim/Makefile by adding this line this line:
CNY_PDK_TB_USER_VLOG += ./tb_user.v

This will create a vsim.wlf file in the sim directory. You can view the waveform using the terminal command
vsim -view vsim.wlf

Running the Vector Adder Example Application

2012-09-25T23:38:52Z

Cnel711: /* Interactive Mode for ModelSim Simulation */

Section 10.5 of the [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] explains how to run the sample software application. It has been reproduced below in brief.

== Compiling the Project ==
The rev version installed on the Convey machine is from 2012-03-19; to copy the sample app's source code run:
cd ~
mkdir pdk_sample
cp -r /opt/convey/pdk/latest/hc-1/examples/* pdk_sample

To make the sample project, first make sure you have [[Convey environment setup|setup your environment variables]], then run:

cd ~/pdk_sample/cae_pers_vadd/SampleAppVadd/
make

This compiles both an emulator (CaeSimPers) and a C program that makes a coprocessor call to use the vector adder (UserApp.exe).

== Run the Project ==
There are three ways to run your project:
# A software simulation of the FPGA design
# A hardware simulation (ModelSim) of the FPGA design
# The actual implementation (C code, Verilog code). The bitfile was previously compiled, nicknamed, and added to a known file location (/opt/convey/personalties/...).

There are some scripts that can be used to run the various projects.

The '''runcp''' (i.e. run coprocessor) script located in the SampleAppVadd can be used to run the application in HW which sets the appropriate environment variables and runs the UserApp.exe:

./runcp

The '''run''' script located in the SampleAppVadd can be used to run the application using the software simulation of the FPGA design.

./run

Using the "-vsim" option, either script can be used to run the application using the hardware simulation (ModelSim). The "-vsim" option sets the environment variable CNY_CAE_EMULATOR to ./run_simulation:

./runcp -vsim
or
./run -vsim

To summarize the important environment variables:

{| border="1" cellpadding="5" cellspacing="0"
|-
|'''Environment Variables''' || '''Software''' || '''ModelSim''' || '''Hardware'''
|-
|CNY_SIM_THREAD || libcpSimLib2.so || libcpSimLib2.so || ''unset''
|-
|CNY_CAE_EMULATOR || <location for CaeSimPers> || ./run_simulation || ''unset''
|}

=== Interactive Mode for ModelSim Simulation ===
The sample project will default to command line mode when using the -vsim flag. Add the following line in the ./sim/Makefile to have it start in interactive mode:

USER_SIM_OPTIONS = -i

You can find the custom personality under testbench->cae_fpga->ae_top->core->cae_pers. Once you have a wave format that you want to automatically load, save it (File->Save Format).

Alternatively, add the $wlfdumpvars line to the sim/tb_user.v file:
// To trace everything
$wlfdumpvars(0, testbench);
// To trace cae_pers module and 5 levels below
$wlfdumpvars(5,testbench.cae_fpga0.ae_top.core.cae_pers);

Then include that file in the sim/Makefile by adding this line this line:
CNY_PDK_TB_USER_VLOG += ./tb_user.v

This will create a vsim.wlf file in the sim directory. You can view the waveform using the terminal command
vsim -view vsim.wlf

Running Different Bitfiles on each AE

2012-09-25T23:34:57Z

Cnel711:

The PDK is setup to help you rapidly test and develop a single bitfile. Thus, projects requiring multiple bitfiles should have multiple PDK sub-projects.

== Running different bitfiles on each AE ==
Source: http://www.ccm.ece.vt.edu/twiki/bin/view/Main/Convey

The runtime environment supports multiple bitfiles making up a single personality (i.e. different ). There is a script called "mkaetgz" that is installed on the HC-1 system. To use it, you need to create a project for each bitfile. Then run the script to package them into one personality.

/opt/convey/sbin/mkaetgz -h
mkaetgz [-i <initFile>] [-f <file0,file1,...,fileN>] [-F] [-h]
[-o <tgz name>] [-t <tmpDir>] [-v]
-0 <aeImage0> [-1 <aeImage1> -2 <aeImage2> -3 <aeImage3>]

For example:
mkaetgz -i /opt/convey/pdk/2010_08_09/doc/cae_init.txt -0 cae_fpga0.bit -1 cae_fpga1.bit -2 cae_fpga2.bit -3 cae_fpga3.bit

Note: mkaetgz does not exist on our machine.

Main Page

2012-09-25T23:32:14Z

Cnel711: /* Convey HC-1 Tutorials */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Running the Vector Adder Example Application]]
* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]
* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]

Using ISE's Core Generator to build FIFOs and other IP cores

2012-09-25T23:28:40Z

Cnel711:

# Open Xilinx's ISE from the terminal (make sure your [[Convey environment setup | environmental variables]] are set):
ise &
# Create or open a project. The devices on the HC-1 and HC-2 are Virtex 5 FPGAs (xc5vlx330, -2, ff1760).
# Open the Core Generator (Tools -> Core Generator...)
# Create a new Core Generator project.
## Part
### Family: Virtex5
### Device: xc5vlx330
### Package: ff1760
### Speed: -2
## Generation
### Simulation Model: Structural
# Generate you IP Cores!
# Copy the .ngc, .v, and .xco to the coregen folder in your PDK project

Convey environment setup

2012-09-25T23:23:06Z

Cnel711:

Please update this document if you think you have a better login setup. Also update this document if the software changes.

You'll want to copy the two files below into to your home directory: '''Xilinx_Env''' and '''cny_Env'''. In addition, edit your .bash_profile to source the files. You can always check to see if your environment is correctly setup by running:

env | grep "CNY"

=== cny_Env ===
#General envs to setup
export CNY_PDK=/opt/convey/pdk
export CNY_PDK_REV=2011_11_22
export CNY_PDK_HDLSIM=Mentor
export CNY_PDK_SIMMODE=64

# For running SW model or Modelsim
# export CNY_SIM_THREAD=libcpSimLib2.so

# For running on HW
export CNY_SIM_THREAD=

# for software emulation
# export CNY_CAE_EMULATOR=<loction of CaeSimPers>
# Example location ~/temp_sample_app/cae_pers_vadd/CaeSimPers/CaeSimPers

# for Modelsim simulation
#export CNY_CAE_EMULATOR=./run_simulation

#for running on HW
export CNY_CAE_EMULATOR=

#see Chap 12 of Convey Programmers Guide v1.8 for more environment variables

=== Xilinx_Env ===
source /remote/Xilinx/13.4/settings64.sh
export PATH=$PATH:/remote/Modelsim/10.1c/modeltech/linux_x86_64/
export LM_LICENSE_FILE=1717@io.ece.iastate.edu:27006@io.ece.iastate.edu

== Editing .bash_profile ==
Adding the following lines to your '''.bash_profile''' file will prevent you from having to source these files every time you login. The file is located in your home directory (use '''ls -a''' to view hidden files that start with '.'). It is assumed that you have copied the two scripts above to your home directory.

=== .bash_profile ===
# .bash_profile

# Get the aliases and functions
if [ -f ~/.bashrc ]; then
. ~/.bashrc
fi

# User specific environment and startup programs

PATH=$PATH:$HOME/bin:.

export PATH

# setup convey aliases
source cny_Env
source Xilinx_Env

=== Ensure You're Using Bash ===
echo $SHELL

If you are not using bash, you can set your default shell to bash at [https://weblogin.iastate.edu/cgi-bin/index.cgi] by going to Manage User ->
View/Edit your Linux login shell -> Select /bin/bash

Using ISE's Core Generator to build FIFOs and other IP cores

2012-09-25T23:22:02Z

Cnel711: New page: # Open Xilinx's ISE from the terminal (make sure your environmental variables are set): ise &

# Open Xilinx's ISE from the terminal (make sure your environmental variables are set):
ise &

Running Different Bitfiles on each AE

2012-09-25T23:21:12Z

Cnel711: New page: == Running different bitfiles on each AE == Source: http://www.ccm.ece.vt.edu/twiki/bin/view/Main/Convey The runtime environment supports multiple bitfiles making up a single personality ...

== Running different bitfiles on each AE ==
Source: http://www.ccm.ece.vt.edu/twiki/bin/view/Main/Convey

The runtime environment supports multiple bitfiles making up a single personality (i.e. different ). There is a script called "mkaetgz" that is installed on the HC-1 system. To use it, you need to create a project for each bitfile. Then run the script to package them into one personality.

/opt/convey/sbin/mkaetgz -h
mkaetgz [-i <initFile>] [-f <file0,file1,...,fileN>] [-F] [-h]
[-o <tgz name>] [-t <tmpDir>] [-v]
-0 <aeImage0> [-1 <aeImage1> -2 <aeImage2> -3 <aeImage3>]

For example:
mkaetgz -i /opt/convey/pdk/2010_08_09/doc/cae_init.txt -0 cae_fpga0.bit -1 cae_fpga1.bit -2 cae_fpga2.bit -3 cae_fpga3.bit

Note: mkaetgz does not exist on our machine.

Main Page

2012-09-25T22:59:17Z

Cnel711: /* Convey HC-1 Tutorials */

== Articles ==
=== Convey HC-1 Tutorials ===
* [[Connecting to convey-1.ece.iastate.edu]]
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]]
* [[Running the Vector Adder Example Application]]
* [[Analyze the Simpleton Basic App]]
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]
* [[Using a Custom Bitfile in C Code]]
* [[Adding VHDL Files to a Project]]
* [[The Verilog Hardware Interface for CAE]]
* [[Using ISE's Core Generator to build FIFOs and other IP cores]]
* [[Running Different Bitfiles on each AE]]
* [[Using SPAT]]
* [[Using GPROF]]
* [[Convey vector example | Example of Loop Unrolling using FPGA]]
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]

== Reference Manuals ==
=== Convey ===
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]

The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey's Support Site]

=== CUDA ===
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]

==Links==
* [http://memocode.irisa.fr MemoCODE 2012]
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]

* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]

=== Other Articles ===
* [[Assignment|Assignments]]
* [[A quick start on CUDA]]

== Helpful Guides ==
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial]
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]

== Readings for Memocode 2012 ==
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]

== Spring 2012 Teams ==
* [[Team Gryffindor]]
* [[Team Slytherin]]
* [[Team 142857]]

Tutorial: Creating a Custom Bitfile

2012-09-24T16:55:03Z

Cnel711: /* Device Usage Statistics */

This page covers the creation and installation of a custom personality/bitfile (a modification of the vector adder sample project).

== Building a Bitfile ==
Copy the newest version of the [[Running the Vector Adder Example Application#Compiling the Project|example project]] and set your [[Convey environment setup|environment variables]] if you have not done so already. You can make a small modification to the verilog code if you wish, such as making it a vector subtractor instead of a vector adder.

Next, compile your bitfile:

cd ~/pdk_sample/cae_vadd/phys
make

The bitfile will take a long time to create (while the Reference Manual states 2 to 4 hours, it may take much longer). Be patient.

Next, package your bitfile using the command:

make release

=== FPGA Usage Statistics ===

The device usage statistics are displayed on the terminal while building the bitfile. The log is saved to disk at:

{project directory}/phys/cae_fpga.map

Search the end of the log file for "Design Summay" for a percentage break down in LUT, Flip flop, and BRAM usage.

== Choose a New Signature ==
Custom personalities should not use the default PDK signature (4.1.1.1.0). Choose a new signature between 65000 and 65535. In this example, we will use 65123.1.1.1.0.

You will need to create a new directory and copy the pertinent files to this directory:

cd /opt/convey/personalities
mkdir 65123.1.1.1.0
cd 65123.1.1.1.0

cp /home/PROJECT_RELEASE/DATE/cae_fpga.tgz ./ae_fpga.tgz

This is the only required file, but you may copy PersDesc.dat from the default PDK folder to your new folder and uncomment additional custom instructions you have used.

cp /opt/convey/personalities/4.1.1.1.0/PersDesc.dat ./

Instead of adding a new directory to Convey's personality folder as done above, you may set the CNY_PERSONALITY_PATH environment variable to any directory, i.e.

export CNY_PERSONALITY_PATH=/home/PROJECT_PATH/
or
setenv CNY_PERSONALITY_PATH /home/PROJECT_PATH/

The default when the CNY_PERSONALITY_PATH is not set is to use the /opt/convey/personalities folder.

You will also need to update the ''customdb'' file in /opt/convey/personalities (or create your own customdb file in your user defined personalities folder). This file is used by the cny_get_signature function and converts strings to a signature number. Our customdb file contains the following text:

65123.1.1.1.0,subtractor

Finally, there are certain places in the code where you should ensure that the signature has been updated.

* In the simulator (/sim/CaeIsaVadd.cpp), update: '''#define PERS_SIGN_CAE 0xfe63001000101000LL''', where 0xfe63 is the hex value for your signature (65123).
* In the C code, (SampleAppVadd/UserApp.c) update: '''cny_get_signature("subtractor", &sig, &sig2, &stat);''', where "subtractor" is the pseudo name of your CAE given in the customdb file.
* In the assembly code, (SampleAppVadd/cpVadd.s) update the signature directive: '''.signature pdk=65123'''

When you change the personalities directory, flush the MP cache. This will unload the current bitfile:

/opt/convey/sbin/mpcache -f

You can also add a signature, and preload a given bitfile by using the commands:

/opt/convey/sbin/mpcache -add -S<personality>
/opt/convey/sbin/mpcache -load -S<personality>

Additional details are available in Appendix D of the [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]].

== See Also ==
* [[Using a Custom Bitfile in C Code]]

== References ==
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] - Sections 9.4.6, 9.4.7, 10, Appendix D