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Welcome to the main wiki page for CprE 488!

We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the MediaWiki page for further details on how to edit.

Useful Documentation

VHDL:
Free Range VHDL Reference Guide

Dr. Jones' Practical VHDL Overview


Tools:
EDK User Guide

EDK Profiling Guide

ZedBoard Tricks and Tips

Auto-loading a design using the sdcard. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order:

  1. A First Stage Boot Loader (FSBL) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile.
  2. A system.bit file created during the conventional XPS build process.
  3. An application that will be loaded after the bitfile programming.

Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build.

Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard.

XPS Tricks and Tips

SDK Tricks and Tips

Matching a BSP to a software project. When an XPS system is exported to SDK, a Board Support Package (BSP) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries.

MP-1 Frequently Asked Questions (FAQ)

Q: How do I bind a transmitter to the quad receiver?

A: Follow this YouTube Link [1]


Q: How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project?

A: XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes.


Q: What is the MPD file format? How do I add my external signals to the auto-generated IP core?

A: Check out the EDK Platform Specification Reference Manual - the MPD file syntax starts on page 27.

MP-0 Frequently Asked Questions (FAQ)

Q: How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there.

A: For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal.


Q: I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next?

A: There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data.


Q: I can't see all the signals that are being discussed in the MP-0 document. What gives?

A: Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default".


Q: What do a correct v_sync and h_sync look like?

A: Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet.


Q: I don't understand whether or not I need to connect signal X in component Y.

A: Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8.


Q: This assignment is too hard!

A: Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs.

General Software Help

Remote Linux access:

Project Ideas